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SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 1 preliminary version 0.1 SN8P1929 user?s manual preliminary specification version 0.2 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or desig n. sonix does not assume any liability arising out of the application or use of an y product or circuit described her ein; neither does it convey a ny license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems inten ded, for surgical implant into the body, or other applications intended to suppor t or sustain life, or for any other application in which the fai lure of the sonix product could create a situation where personal injury or death may occu r. should buyer purchase or use sonix products for any such uni ntended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subs idiaries, affiliates and distri butors harmless against all claims, cost, damages, and expenses, and re asonable attorney fees arising out of, dire ctly or indirectly, any claim of pers onal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 2 preliminary version 0.1 amendent history version date description ver 0.1 july 2008 first issue. ver 0.2 july 2008 update pin assignment in lqfp package
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 3 preliminary version 0.1 table of content amendent history........................................................................................................................ ........ 2 1 1 1 product overview............................................................................................................... .......... 8 1.1 selection table......................................................................................................................... 8 1.2 features ................................................................................................................... ..................... 8 1.3 system block diagram .......................................................................................................... 9 1.4 pin assignment ..................................................................................................................... .... 10 1.5 pin descriptions................................................................................................................... .... 11 1.6 pin circuit diagrams............................................................................................................. 12 2 2 2 central processor unit (cpu) .............................................................................................. 13 2.1 memory map............................................................................................................................ ... 13 2.1.1 program memory (rom) ................................................................................................. 13 2.1.2 reset vector (0000h) ........................................................................................................ 14 2.1.2.1 interrupt vector (0008h)......................................................................................... 15 2.1.2.2 look-up table description.................................................................................... 17 2.1.2.3 jump table description ........................................................................................... 19 2.1.2.4 checksum calculation........................................................................................... 21 2.1.3 code option table ........................................................................................................... 22 2.1.4 data memory (ram)........................................................................................................... 23 2.1.5 system register................................................................................................................ .24 2.1.5.1 system register table ............................................................................................ 24 2.1.5.2 system register description ............................................................................... 24 2.1.5.3 bit definition of system register....................................................................... 25 2.1.5.4 accumulator ............................................................................................................ ... 27 2.1.6 program flag ................................................................................................................... .28 2.1.6.1 program counter....................................................................................................... 2 9 2.1.7 h, l registers................................................................................................................. ..... 31 2.1.7.1 x registers ............................................................................................................ ......... 33 2.1.7.2 y, z registers......................................................................................................... ........ 34 2.1.8 r registers.................................................................................................................... ....... 35 2.2 addressing mode .................................................................................................................... 36 immediate addressing mode........................................................................................... 36 directly addressing mode .............................................................................................. 36 indirectly addressing mode .......................................................................................... 36 2.3 stack operation...................................................................................................................... 37 2.3.1 overview ....................................................................................................................... ....... 37 2.3.2 stack registers ................................................................................................................ .38
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 4 preliminary version 0.1 2.3.3 stack operation example............................................................................................. 39 3 3 3 reset .......................................................................................................................... ........................... 40 3.1 overview................................................................................................................... .................. 40 3.2 power on reset......................................................................................................................... 4 1 3.3 watchdog reset...................................................................................................................... 41 3.4 brown out reset ..................................................................................................................... 42 3.4.1 brown out description ................................................................................................. 42 3.4.2 the system operating voltage decsription........................................................ 43 3.4.3 brown out reset improvement.................................................................................. 43 3.5 external reset ........................................................................................................................ 45 3.6 external reset circuit ....................................................................................................... 45 3.6.1 simply rc reset circuit ........................................................................................................ ... 45 3.6.2 diode & rc reset circuit ....................................................................................................... .46 3.6.3 zener diode reset circuit ...................................................................................................... .. 46 3.6.4 voltage bias reset circuit..................................................................................................... ... 47 3.6.5 external reset ic.............................................................................................................. ........ 48 4 4 4 system clock ................................................................................................................... ............... 49 4.1 overview................................................................................................................... .................. 49 4.2 clock block diagram .......................................................................................................... 49 4.3 oscm register ....................................................................................................................... .... 50 4.4 system high clock ................................................................................................................. 51 4.4.1 internal high rc............................................................................................................... 51 4.4.2 external high clock...................................................................................................... 51 4.4.2.1 crystal/ceramic........................................................................................................ . 52 4.4.2.2 external clock signal........................................................................................... 52 4.5 system low clock .................................................................................................................. 53 4.5.1.1 crystal ................................................................................................................ ............ 53 4.5.1.2 rc type................................................................................................................ ................ 53 4.5.2 system clock measurement ........................................................................................ 55 5 5 5 system operation mode .......................................................................................................... .56 5.1 overview................................................................................................................... .................. 56 5.2 system mode switching....................................................................................................... 57 5.3 wakeup ..................................................................................................................... .................... 59 5.3.1 overview ....................................................................................................................... ....... 59 5.3.2 wakeup time.................................................................................................................... .... 59 5.3.3 p1w wakeup control register ................................................................................... 60 6 6 6 interrupt...................................................................................................................... ..................... 61
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 5 preliminary version 0.1 6.1 overview................................................................................................................... .................. 61 6.2 inten interrupt enable register................................................................................... 61 6.3 intrq interrupt request register ................................................................................ 63 6.4 gie global interrupt operation .................................................................................... 63 6.5 push, pop routine .................................................................................................................... 65 6.6 int0 (p0.0) interrupt operation......................................................................................... 66 6.7 int1 (p0.1) interrupt operation......................................................................................... 67 6.8 t0 interrupt operation ....................................................................................................... 68 6.9 tc0 interrupt operation..................................................................................................... 69 6.10 tc1 interrupt operation..................................................................................................... 70 6.11 multi-interrupt operation............................................................................................... 71 7 7 7 i/o port ....................................................................................................................... ......................... 73 7.1 i/o port mode ........................................................................................................................... .. 73 7.2 i/o pull up register ................................................................................................................ 74 7.3 i/o port data register .......................................................................................................... 75 8 8 8 timers ......................................................................................................................... ......................... 76 8.1 watchdog timer (wdt) ......................................................................................................... 76 8.2 timer 0 (t0) ........................................................................................................................... ........ 78 8.2.1 overview ....................................................................................................................... ....... 78 8.2.2 t0m mode register........................................................................................................... 79 8.2.3 t0c counting register................................................................................................... 80 8.2.4 t0 timer operation sequence ..................................................................................... 81 8.3 timer/counter 0 (tc0) ............................................................................................................ 82 8.3.1 overview ....................................................................................................................... ....... 82 8.3.2 tc0m mode register ........................................................................................................ 83 8.3.3 tc1x8, tc0x8, tc0gn flags .............................................................................................. 84 8.3.4 tc0c counting register ................................................................................................ 85 8.3.5 tc0r auto-load register .............................................................................................. 87 8.3.6 tc0 clock frequency ou tput (buzzer) .................................................................. 88 8.3.7 tc0 timer operation sequence .................................................................................. 89 8.4 timer/counter 1 (tc1) ............................................................................................................ 91 8.4.1 overview ....................................................................................................................... ....... 91 8.4.2 tc1m mode register ........................................................................................................ 92 8.4.3 tc1x8, tc0x8, tc0gn flags .............................................................................................. 93 8.4.4 tc1c counting register ................................................................................................ 94 8.4.5 tc1r auto-load register .............................................................................................. 96 8.4.6 tc1 clock frequency ou tput (buzzer) .................................................................. 97 8.4.7 tc1 timer operation sequence .................................................................................. 98
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 6 preliminary version 0.1 8.5 pwm0 mode ........................................................................................................................... ..... 100 8.5.1 overview ....................................................................................................................... ..... 100 8.5.2 tc0irq and pwm duty .................................................................................................... 101 8.5.3 pwm program example ................................................................................................ 101 8.5.4 pwm0 duty changing notice ..................................................................................... 102 8.6 pwm1 mode ........................................................................................................................... ..... 103 8.6.1 overview ....................................................................................................................... ..... 103 8.6.2 tc1irq and pwm duty .................................................................................................... 104 8.6.3 pwm program example ................................................................................................ 104 8.6.4 pwm1 duty changing notice ..................................................................................... 105 9 9 9 lcd driver ..................................................................................................................... .................. 106 9.1 lcdm1 register....................................................................................................................... 106 9.2 option register description........................................................................................... 106 9.3 lcd timing ......................................................................................................................... ........ 107 9.4 lcd ram location ................................................................................................................. 109 9.5 lcd c ircuit ............................................................................................................................... ... 110 1 1 1 0 0 0 in system program rom ..................................................................................................... 112 10.1 overview.................................................................................................................. ................. 112 10.2 romadrh/romadrl register........................................................................................... 112 10.3 romdah/romadl registers.............................................................................................. 112 10.4 romcnt registers and romwrt instruction ........................................................... 113 10.5 isp rom routine example .................................................................................................. 114 1 1 1 1 1 1 charge-pump, pgia and adc .............................................................................................. 115 11.1 overview.................................................................................................................. ................. 115 11.2 analog input.......................................................................................................................... . 115 11.3 v oltage c harge p ump / r egulator (cpr) ............................................................................... 116 11.3.1 cpm-charge pump mode register........................................................................................ 116 11.3.2 cpcks-charge pump clock register ................................................................................... 118 11.4 pgia -p rogrammable g ain i nstrumentation a mplifier ....................................................... 120 11.4.1 ampm- amplifier mode register........................................................................................... 120 11.4.2 ampcks- pgia clock selection ................................................................................. 121 11.4.3 ampchs-pgia channel selection ............................................................................. 122 11.4.4 temperature sensor (ts)........................................................................................................ 123 11.5 16-b it adc ............................................................................................................................ ........ 126 11.5.1 adcm- adc mode register .................................................................................................. 126 11.5.2 adcks- adc clock register ................................................................................................ 129 11.5.3 adcdl- adc low-byte data register ................................................................................. 130 11.5.4 adcdh- adc high-byte data register ............................................................................... 130
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 7 preliminary version 0.1 11.5.5 dfm-adc digital filter mode register ............................................................................... 131 11.5.6 lbtm : low battery detect register ..................................................................................... 134 11.5.7 analog setting and application.............................................................................................. 135 1 1 1 2 2 2 application circuit............................................................................................................ .. 137 12.1 s cale (l oad c ell ) a pplication c ircuit ................................................................................... 137 12.2 t hermometer a pplication c ircuit ........................................................................................... 138 1 1 1 3 3 3 instruction table .............................................................................................................. ... 139 1 1 1 4 4 4 development tools .............................................................................................................. 140 14.1 d evelopment t ool v ersion ....................................................................................................... 140 14.1.1 ice (in circuit emulation) ..................................................................................................... . 140 14.1.2 otp writer ..................................................................................................................... ........ 140 14.1.3 ide (integrated development environment) ......................................................................... 140 14.2 otp p rogramming p in to t ransition b oard m apping ........................................................... 141 14.2.1 the pin assignment of easy and mp ez writer transition board socket:.............................. 141 14.2.2 the pin assignment of writer v3.0 transition board socket:.................................................. 141 14.2.3 SN8P1929 series programming pin mapping: ..................................................................... 142 1 1 1 5 5 5 electrical characteristic ............................................................................................ 143 15.1 absolute maximum rating .............................................................................................. 143 15.2 electrical characteristic............................................................................................. 143 1 1 1 6 6 6 package information ......................................................................................................... 146 16.1 lqfp 80 pin ............................................................................................................................ ...... 146 1 1 1 7 7 7 marking definition............................................................................................................. .. 147 17.1 introduction .............................................................................................................. ............ 147 17.2 marking indetification system.................................................................................... 147 17.3 marking example ................................................................................................................. 148 17.4 datecode system .................................................................................................................. 148
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 8 preliminary version 0.1 1 1 1 product overview 1.1 selection table timer chip rom ram stack lcd t0 tc0 tc1 i/o adc (bit) pwm buzzer sio wakeup pin no. package sn8p1908 8k*16 512*8 8 4*24 v v v 17 16 2 - 7 lqfp64 sn8p1909 8k*16 512*8 8 4*32 v v v 20 16 2 1 7 lqfp80 sn8p1919 6k*16 256*8 8 4*32 v v v 22 16 2 - 7 lqfp80 SN8P1929 4k*16 256*8 8 4*24 v v v 16 16 2 - 6 lqfp80/64 table 1-1 selection table of SN8P1929 1.2 features memory configuration five interrupt sources otp rom size: 4k * 16 bits three internal interrupts: t0, tc0, tc1 ram size: 256 * 8 bits (bank 0, bank 1) two external interrupts: int0, int1 8-levels stack buffer single power supply: 2.4v ~5.5v lcd ram size: 4*24 bits on-chip watchdog timer i/o pin configuration on-chip charge-pump re g ulator with 3.8v volta g e output and 10ma driven current. input only: p0 on chip regulator with 3.0v/2.4v/1.5v output voltage bi-directional: p1, p2, p4, p5 on-chip 1.2v band gap reference for batter y monitor. wakeup: p0, p1 on chip voltage comparator. pull-up resisters: p0, p1, p2, p4, p5 build in adc reference voltage v(r+,r- ) =0.8v , 0.64v or 0.4v. external interrupt: p0 build in temperature sensor. powerful instructions lcd driver: four clocks per instruction cy cle 1/3 or 1/2 bias voltage. all instructions are one word length 4 common * 24 segment most of instructions are 1 cycle only. maximum instructio n cycle is ?2?. dual clock system offers four operating modes jmp instruction jumps to all rom area. internal high clock: rc type up to 16 mhz all rom area look-up table function (movc) external high clock: crystal type up to 8 mhz normal mode: both high and low clock active. programmable gain instrumentation amplifier slow mode: external low clock and internal low rc clock. gain option: 1x/12.5x/50x/100x/200x green mode: period wake up by t0 and tc0 sleep mode: both high and low clock stop. 16-bit delta-sigma adc with 14-bit noise free package three adc channel configurations: lqfp80/ lqfp64/dice two fully differential channel one differential and two single-ended channels four single-ended channels
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 9 preliminary version 0.1 1.3 system block diagram figure 1-1 simplified system block diagram interrupt control external high osc. acc external low osc. internal high rc timing generator ram system registers lvd (low voltage detector) watchdog timer pgia comparator timer & counter p0 p4 p5 16-bit adc charge pump regulator alu pc flags ir otp rom avddcp ai+/ai- avddr ave+ lbtin2/1 r+/r- internal reference internal adc channel for battery detect p1 p2
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 10 preliminary version 0.1 1.4 pin assignment SN8P1929 lqfp80 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 com1 1 o 60 seg18 com0 2 59 seg19 vlcd 3 58 seg20 v3 4 57 seg21 v2 5 56 seg22 v1 6 55 seg23 r+ 7 54 nc r- 8 53 nc x+ 9 52 reset/vpp x- 10 SN8P1929 51 vss ai2+ 11 50 p5.4/pwm0/bz0 ai2- 12 49 p5.3/pwm1/bz1 ai1+ 13 48 p5.2 ai1- 14 47 p5.1 avss 15 46 p5.0 acm 16 45 p4.2/lbtin2 avddr 17 44 p4.1/lbtin1 ave+ 18 43 p4.0 avddcp 19 42 nc nc 20 41 nc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 nc nc c+ vdd c- vss lxin lxout p2.0/xin p2.1/xout vdd p0.0/int0 p0.1/int1 p1.0/pgclk p1.1/otpclk p1.2/shiftdata p1.3/pbd nc nc nc
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 11 preliminary version 0.1 1.5 pin descriptions pin name type description vdd, vss, avss p power supply input pi ns for digital / analog circuit. vlcd p lcd power supply input avddr p regulator power output pin, voltage=3.8v. ave+ p regulator output =3.0v /2.4v/1.5v for sensor. maximum output current=10 ma acm p band gap voltage output =1.2v avddcp p charge pump voltage output. ( c onnect a 10uf or hi gher capacitor to ground) r+ ai positive reference input r- ai negative reference input x+ ai positive adc differential input, a 0.1uf capacitor connect to pin x- x- ai negative adc differential input ai1+,ai2+ ai positive analog input channel ai-, ai2- ai negative analog input channel c+ a positive capacitor terminal for charge pump regulator c- a negative capacitor terminal for charge pump regulator vpp/ rst p, i otp rom programming pin. system reset input pin. schmitt trigger st ructure, active ?low?, normal stay to ?high?. xin, xout i, o external high cl ock oscillator pins. no rc mode p0.0 / int0 i p0.0 shared with int0 trigger pin (schmitt trigger) / built-in pull-up resisters. p0.1 / int1 i p0.1 shared with int0 trigger pin (schmitt trigger) / built-in pull-up resisters. p1 [3:0] i/o p1.0 ~ p1.3 bi-direction pins / wakeup pins/ built-in pull-up resisters. p2 [1:0] i/o p2.0 ~ p2.1 bi-direction pins / built- in pull-up resisters. shared with xin/xout p4 [2:0] i/o bi-direction pins / built-in pull-up resisters p5 [2:0] i/o bi-direction pins / built-in pull-up resisters. p5 [4:3] i/o bi-direction pins / built-in pull-up resisters / shared with pwm, tcout lbtin1/2 i low battery detect input pins shared with p4.1, p4.2 com [3:0] o com0~com3 lcd driver common port seg0 ~ seg23 o lcd driver segment pins.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 12 preliminary version 0.1 1.6 pin circuit diagrams port 0 structure: port1, port4 and port5 structure: port2 structure: pull-up pin pnur input bus pull-up pin output latch pnm, pnur input bus pnm output bus oscillator code option int. osc. pull-up pin output latch pnm, pnur input bus pnm output bus
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 13 preliminary version 0.1 2 2 2 central processor unit (cpu) 2.1 memory map 2.1.1 program memory (rom) ) 4k words rom rom 0000h reset vector user reset vector 0001h jump to user start address 0002h jump to user start address 0003h general purpose area jump to user start address 0004h 0005h 0006h 0007h reserved 0008h interrupt vector user interrupt vector 0009h user program . . 000fh 0010h 0011h . . ffeh general purpose area end of user program fffh code option code option address.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 14 preliminary version 0.1 2.1.2 reset vector (0000h) a one-word vector address area is used to execute system reset. ) power on reset (nt0=1, npd=0). ) watchdog reset (nt0=0, npd=0). ) external reset (nt0=1, npd=1). after power on reset, external reset or watchdog timer over flow reset, then the chip will restart the program from address 0000h an d all system registers will be set as default values . it is easy to know rese t status from nt0, npd flags of pflag register. the following example shows the way to define the reset vector in the program memory. ? example: defining reset vector org 0 ; 0000h jmp start ; jump to user program address. ? org 10h start: ; 0010h, the head of user program. ? ; user program ? endp ; end of program
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 15 preliminary version 0.1 2.1.2.1 interrupt vector (0008h) a 1-word vector address area is used to execute interr upt request. if any interrupt se rvice executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define the interr upt vector. the following example shows the wa y to define the interrupt vector in the program memory. ? note: ?push?, ?pop? instructions only process 0x80~ 0x87 working registers a nd pflag register. users have to save and load acc by program as interrupt occurrence. ? example: defining interrupt vector. the in terrupt service routine is following org 8. .data accbuf ds 1 ; define accbuf for store acc data. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. b0xch a, accbuf ; save acc in a buffer push ; save 0x80~0x87 working registers and pflag register to buffers. ? ? pop ; load 0x80~0x87 working registers and pflag register from buffers. b0xch a, accbuf ; restore acc from buffer reti ; end of interrupt service routine ? start: ; the head of user program. ? ; user program ? jmp start ; end of user program ? endp ; end of program
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 16 preliminary version 0.1 ? example: defining interrupt vector. the interru pt service routine is following user program. .data accbuf ds 1 ; define accbuf for store acc data. .code org 0 ; 0000h jmp start ; jump to user program address. ? org 8 ; interrupt vector. jmp my_irq ; 0008h, jump to interrupt service routine address. org 10h start: ; 0010h, the head of user program. ? ; user program. ? ? jmp start ; end of user program. ? my_irq: ;the head of interrupt service routine. b0xch a, accbuf ; save acc in a buffer push ; save 0x80~0x87 working registers and pflag register to buffers. ? ? pop ; load 0x80~0x87 working registers and pflag register from buffers. b0xch a, accbuf ; restore acc from buffer reti ; end of interrupt service routine. ? endp ; end of program. ? note: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 0000h is a ?jmp? instruction to make the program starts from the beginning. 2. the address 0008h is interrupt vector. 3. user?s program is a loop routine for main purpose application.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 17 preliminary version 0.1 2.1.2.2 look-up table description in the rom?s data lookup function, x register is pointed to high byte address (bit 16~bit 23), y register is pointed to middle byte address (bit 8~bit 15) and z register is pointed to low byte address (bit 0~bit 7) of rom. after movc instruction executed, the low-byte data will be stored in acc and hi gh-byte data stored in r register. ? example: to look up the rom data located ?table1?. b0mov x, #table1$h ; to set lookup table1?s high address b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h ; increment the index address for next address. incms z ; z+1 jmp @f ; z is not overflow. incms y ; z is overflow, y=y+1. jmp @f ; y is not overflow. incms x ; y is overflow, x=x+1. nop ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? ? note: the x, y registers will not increase automatically when y, z registers crosses boundary from 0xff to 0x00. therefore, user must take care such situation to avoid loop-up table errors. if z register is overflow, y register must be added one. if y regist er is overflow, x register must be added one. the following inc_xyz macro shows a simple method to process x, y and z registers automatically. ? example: inc_xyz macro. inc_xyz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 jmp @f ; not overflow incms x ; x+1 nop ; not overflow @@: endm
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 18 preliminary version 0.1 ? example: modify above example by ?inc_xyz? macro. b0mov x, #table1$h ; to set lookup table1?s high address b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table1?s low address. movc ; to lookup data, r = 00h, acc = 35h inc_xyz ; increment the index address for next address. ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? ; table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ? the other example of loop-up table is to add x, y or z index register by accumulator. please be careful if ?carry? happen. ? example: increase y and z register by b0add/add instruction. b0mov x, #table1$h ; to set lookup table1?s high address b0mov y, #table1$m ; to set lookup table1?s middle address b0mov z, #table1$l ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. jmp getdata ; y is not overflow. incms x ; y is overflow, x=x+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012 ? table1: dw 0035h ; to define a word (16 bits) data. dw 5105h dw 2012h ?
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 19 preliminary version 0.1 2.1.2.3 jump table description the jump table operation is one of multi-address jumpin g function. add low-byte program counter (pcl) and acc value to get one new pcl. the new program counter (pc) points to a series jump instructions as a listing table. it is easy to make a multi-jump program depends on the value of the accumulator (a). when carry flag occurs after ex ecuting of ?add pcl, a?, it will not affect p ch register. users have to check if the jump table leaps over the rom page boundary or the listing file generated by sonix assembly software. if the jump table leaps over the rom page boundary (e.g. from xxffh to xx0 0h), move the jump table to the top of next program memory page (xx00h). here one page mean 256 words. ? note: program counter can?t carry from pcl to pch when pcl is overflow after executin g addition instruction. ? example: jump table. org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, the pch can?t be changed. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point in following example, the jump table starts at 0x00fd. w hen execute b0add pcl, a. if acc = 0 or 1, the jump table points to the right address. if the acc is larger then 1 will cause error be cause pch doesn't incr ease one automatically. we can see the pcl = 0 when acc = 2 but the pch still keep in 0. the progra m counter (pc) will point to a wrong address 0x0000 and crash system ope ration. it is important to check whethe r the jump table crosses over the boundary (xxffh to xx00h). a good coding style is to put t he jump table at the start of rom boundary (e.g. 0100h). ? example: if ?jump table? crosses over rom boundary will cause errors. rom address ? ? ? 0x00fd b0add pcl, a ; pcl = pcl + ac c, the pch can?t be changed. 0x00fe jmp a0point ; acc = 0 0x00ff jmp a1point ; acc = 1 0x0100 jmp a2point ; acc = 2 ? jump table cross boundary here 0x0101 jmp a3point ; acc = 3 ? ?
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 20 preliminary version 0.1 sonix provides a macro for safe jump table function. th is macro will check the rom boundary and move the jump table to the right position automatically. the side e ffect of this macro maybe wastes some rom size. ? example: if ?jump table? crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif add pcl, a endm ? note: ?val? is the number of the jump table listing number. ? example: ?@jmp_a? application in sonix macro file called ?macro3.h?. b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point jmp a4point ; acc = 4, jump to a4point if the jump table position is across a rom boundary (0x00ff~ 0x0100), the ?@jmp_a? macro will adjust the jump table routine begin from next ram boundary (0x0100). ? example: ?@jmp_a? operation. ; before compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x00fd jmp a0point ; acc = 0, jump to a0point 0x00fe jmp a1point ; acc = 1, jump to a1point 0x00ff jmp a2point ; acc = 2, jump to a2point 0x0100 jmp a3point ; acc = 3, jump to a3point 0x0101 jmp a4point ; acc = 4, jump to a4point ; after compiling program. rom address b0mov a, buf0 ; ?buf0? is from 0 to 4. @jmp_a 5 ; the number of the jump table listing is five. 0x0100 jmp a0point ; acc = 0, jump to a0point 0x0101 jmp a1point ; acc = 1, jump to a1point 0x0102 jmp a2point ; acc = 2, jump to a2point 0x0103 jmp a3point ; acc = 3, jump to a3point 0x0104 jmp a4point ; acc = 4, jump to a4point
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 21 preliminary version 0.1 2.1.2.4 checksum calculation the last rom address is reserved area. user should avoi d these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksum from 00h to the end of user?s code. mov a,#end_user_code$l b0mov end_addr1, a ; save low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2, a ; save middle end address to end_addr2 clr y ; set y to 00h clr z ; set z to 00h @@: movc b0bset fc ; clear c flag add data1, a ; add a to data1 mov a, r adc data2, a ; add r to data2 jmp end_check ; check if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; if z = 00h increase y end_check: mov a, end_addr1 cmprs a, z ; check if z = low end address jmp aaa ; if not jump to checksum calculate mov a, end_addr2 cmprs a, y ; if yes, check if y = middle end address jmp aaa ; if not jump to checksum calculate jmp checksum_end ; if yes checksum calculated is done. y_add_1: incms y ; increase y nop jmp @b ; jump to checksum calculate checksum_end: ? ? end_user_code: ; label of program end
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 22 preliminary version 0.1 2.1.3 code option table code option content function description ihrc high speed internal 16mhz rc. xin/xout become to p2.0/p2.1 bi-direction i/o pins. high_clk 4m x?tal standard crystal /resonator (e.g. 4m) for external high clock oscillator. enable enable watchdog function watch_dog disable disable watchdog function enable enable rom code security function security disable disable rom code security function always_on force watch dog timer clock source come from int 16k rc. also int 16k rc never stop both in power down and green mode that means watch dog timer will always enable both in power down and green mode. int_16k_rc by_cpum enable or disable internal 16k (@ 3v) rc clock by cpum register enable enable noise filter in high noisy environment. noise filter disable disable noise filter. enable enable low power function to save operating current low power disable disable low power function ? note: 1. in high noisy environment, set watch_dog as ?enable? and int_16k_rc as ?always_on? and enable noise filter is strongly recommended. 2. fcpu code option is only available for high clock. fcpu of slow mode is flosc/4. 3. in high noisy environment, disable ?low power? is strongly recommended. 4. the side effect is to increase the lowest valid working voltage level if enable ?low power? and ?noise filter? code option. 5. enable ?low power? option will reduce operating current except in slow mode.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 23 preliminary version 0.1 2.1.4 data memory (ram) ) 256 x 8-bit ram ram location 000h general purpose area ; 000h~07fh of bank 0 = to store general . ; purpose data (128 bytes). 07fh . 080h system register ; 080h~0ffh of bank 0 = to store system . ; registers (128 bytes). bank 0 0ffh end of bank 0 area 100h general purpose area ; 100h~17fh of bank 1 = to store general . ; purpose data (128 bytes). bank 1 17fh . ; f00h lcd ram area ; bank 15 = to store lcd display data . ; (24bytes). bank 15 f1fh end of lcd ram ;
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 24 preliminary version 0.1 2.1.5 system register 2.1.5.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y x pflag rbank option lcdm1 - - - - - - 9 ampm ampchs ampcks adcm adcks cpm cpcks dfm adcdl adcdh lbtm - - - - - a romadrh romadrl romdah romdal romcnt - - - - - - - - - - - b - - - - - - - - - - - - - - - pedge c p1w p1m p2m p3m - p5m - - intrq inten oscm - - tc0r pcl pch d p0 p1 p2 p3 - p5 - - t0m t 0c tc0m tc0c tc1m tc1c tc1r stkp e p0ur p1ur p2ur p3ur - p5ur @hl @yz - - - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4 h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.1.5.2 system register description l, h = working & @hl addressing register option = rclk options. y, z = working, @yz and rom addressing re gister rbank= ram bank select register pflag = rom page and special flag regist er ampchs = pgia channel selection ampm = pgia mode register adcm = adc?s mode register ampcks = pgia clock selection cpm = charge pump mode adcks = adc clock selection dfm = decimation filter mode cpcks = charge pump clock selection adcdh = adc high-byte data buffer adcdl = adc low-byte data buffer p1w = port 1 wakeup register p n m = port n input/output mode register p n ur = port n pull-up register p n = port n data buffer intrq = i nterrupt request register inten = interrupt enabl e register oscm = osc illator mode register lcdm1= lcd mode register pch, pcl = program counter t0m = timer 0 mode register tc0m = timer/counter 0 mode register t0c = timer 0 counting register tc0c = timer/counter 0 counting register tc1m = timer/counter 1 mode register tc0r = timer/counter 0 auto-reload data buffer tc1c = timer/counter 1 counting register lbtm = low battery detect register stkp = stack pointer buffer stk0~stk7 = stack 0 ~ stack 7 buffer @hl = ram hl indirect addressing index pointer romadrh/l= isp rom address @yz = ram yz indirect addressing index pointer romdah/l= isp rom data r = working register and rom look-up data buffer romcnt = isp rom counter
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 25 preliminary version 0.1 2.1.5.3 bit definition of system register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w name 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 085h xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 r/w x 086h nt0 npd - - - c dc z r/w pflag 087h - - - - rbnks3 rbnks2 rbnks1 rbnks0 r/w rbank 088h rclk r/w option 089h lcdref1 lcdref0 lcdbnk - lcdenb lcdbias r/w lcdm1 090h chpenb bgrenb fds1 fds0 gs2 gs1 gs0 ampenb r/w ampm 091h - - - - chs3 chs2 chs1 chs0 r/w ampchs 092h - - - - - ampcks2 ampcks1 ampcks0 w ampcks 093h - - - - irvs rvs1 rvs0 adcenb r/w adcm 094h adcks7 adcks6 adcks5 adcks4 a dcks3 adcks2 adcks1 adcks0 r/w adcks 095h acmenb avddrenb avenb avesel1 avesel0 cpauto cpon cprenb r/w cpm 096h - - - - cpcks3 cpcks2 cpcks1 cpcks0 r/w cpcks 097h - - - wrs0 drdy r/w dfm 098h adcb9 adcb8 adcb7 adcb6 a dcb5 adcb4 adcb3 adcb2 r adcdl 099h adcb17 adcb16 adcb15 adcb14 a dcb13 adcb12 adcb11 adcb10 r adcdh 09ah - - - - - lbto p 41io lbtenb r/w lbtm 09bh - - - - - - - cpsave r/w cpmtest 0a0h vppchk - - - romadr11 romadr10 romadr9 romadr8 r/w romadrh 0a1h romadr7 romadr6 romadr5 romadr4 rom adr3 romadr2 romadr1 romadr0 r/w romadrl 0a2h romda15 romda14 romda13 romda12 r omda11 romda10 romda9 romda8 r/w romdah 0a3h romda7 romda6 romda5 romda4 ro mda3 romda2 romda1 ro mda0 r/w romdal 0a4h romcnt7 romcnt6 romcnt5 romc nt4 romcnt3 romcnt2 romcnt1 romcnt0 w romcnt 0bfh pedgen - - p00g1 p00g0 - - - r/w pedge 0c0h - - - - p13w p12w p11w p10w w p1w 0c1h - - - - p13m p12m p11m p10m r/w p1m 0c2h - - - - - - p21m p20m r/w p2m 0c4h - - - - - p42m p41m p40m r/w p4m 0c5h - - - p54m p53m p52m p51m p50m r/w p5m 0c8h - tc1irq tc0irq t0irq - - p01irq p00irq r/w intrq 0c9h - tc1ien tc0ien t0ien - - p01ien p00ien r/w inten 0cah wtcks wdrst wdrate cpum1 cpum0 clkmd stphx - r/w oscm 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh - - - - pc11 pc10 pc9 pc8 r/w pch 0d0h - - - - - - p01 p00 r p0 0d1h - - - - p13 p12 p11 p10 r/w p1 0d2h - - - - - - p21 p20 r/w p2 0d4h - - - - - p42 p41 p40 r/w p4 0d5h - - - p54 p53 p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload1 tc1out pwm1out r/w tc1m 0ddh tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 r/w tc1c 0deh tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 r/w tc1r 0dfh gie - - - stkpb2 stkpb1 stkpb0 r/w stkp 0e0h - - - - - - p01r p00r w p0ur 0e1h - - - - p13r p12r p11r p10r w p1ur 0e2h - - - - - - p21r p20r w p2ur 0e4h - - - - - p42r p41r p40r w p4ur 0e5h - - - p54r p53r p52r p51r p50r w p5ur 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h - - - s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h - - - - s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h - - - - s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 26 preliminary version 0.1 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h - - - - s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h - - - - s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2 pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh - - - - s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh - - - - s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0 pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh - - - - s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h ? note: 1. to avoid system error, make sure to put all the ?0? and ?1? as it indicates in the above table . 2. all of register names had been declared in sn8asm assembler. 3. one-bit name had been declared in sn8asm assembler with ?f? prefix code. 4. ?b0bset?, ?b0bclr?, ?bset?, ?bclr? instruct ions are only available to the ?r/w? registers.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 27 preliminary version 0.1 2.1.5.4 accumulator the acc is an 8-bit data register responsible for trans ferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be acce ss by ?b0mov? instruction dur ing the instant addressing mode. ? example: read and write acc value. ; read acc data and store in buf data memory mov buf, a ; write a immediate data into acc mov a, #0fh ; write acc data from buf data memory mov a, buf the system doesn?t store acc and pfla g value when interrupt executed. a cc and pflag data must be saved to other data memories. ?push?, ?pop? save and load 0x80~0x87 system registers data into buffers. users have to save acc data by program. ? example: protect acc and working registers. .data accbuf ds 1 ; define accbuf for store acc data. .code int_service: b0xch a, accbuf ; save acc to buffer. push ; save pflag and working registers to buffer. ? . ? pop ; load pflag and working registers form buffers. b0xch a, accbuf ; load acc form buffer. reti ; exit interrupt service vector ? note: to save and re-load acc data, users must use ?b0xch? instructi on, or else the pflag register might be modified by acc operation.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 28 preliminary version 0.4 2.1.6 program flag the pflag register contains the arithm etic status of alu operat ion, system reset status and lvd detecting status. nt0, npd bits indicate system reset status including po wer on reset, lvd reset, reset by external pin active and watchdog reset. c, dc, z bits indicate t he result status of alu operation. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd reset status 0 0 watch-dog time out 0 1 reserved 1 0 reset by lvd 1 1 reset by external reset pin bit 2 c: carry flag 1 = addition with carry, subtraction without borrowing, ro tation with shifting out logic ?1?, comparison result 0. 0 = addition without carry, s ubtraction with borrowing signal, rotation wi th shifting out logic ?0?, comparison result < 0. bit 1 dc: decimal carry flag 1 = addition with carry from low nibble, s ubtraction without borrow from high nibble. 0 = addition without carry from low nibble, subtraction with borrow from high nibble. bit 0 z: zero flag 1 = the result of an arithmetic/logic/branch operation is zero. 0 = the result of an arithmetic/logic/branch operation is not zero. ? note: refer to instruction set table for detailed information of c, dc and z flags.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 29 preliminary version 0.4 2.1.6.1 program counter the program counter (pc) is a 12-bit binary counter sepa rated into the high-byte 4 and the low-byte 8 bits. this counter is responsible for pointing a location in order to fe tch an instruction for kernel circuit. normally, the program counter is automatically incremented with eac h instruction during program execution. besides, it can be replaced with specific address by execut ing call or jmp instruction. when jmp or call instruction is executed, the desti nation address will be inserted to bit 0 ~ bit 11. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - - 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl ) one address skipping there are nine instructions (cmprs, incs, incms, de cs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. ? ? c0step: nop b0mov a, buf0 ; move buf0 value to acc. b0bts0 fz ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. ? ? c1step: nop if the acc is equal to the immediat e data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step. ? ? c0step: nop
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 30 preliminary version 0.4 if the destination increased by 1, wh ich results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop if the destination decreased by 1, which results underflo w of 0x00 to 0xff, the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. ? ? c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. ? ? c0step: nop
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 31 preliminary version 0.4 ) multi-address jumping users can jump around the mult i-address by either jmp inst ruction or add m, a instruction (m = pcl) to activate multi-address jumping function. program counter supports ?add m,a? , ?adc m,a? and ?b0add m,a? instructions for carry to pch when pcl overflow automatically. for jump t able or others applications, users can calculate pc value by the three instructions and don?t care pcl overflow problem. ? note: pch only support pc up counting result and doesn?t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl?acc, pch keeps value and not change. ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ? ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? ? example: if pc = 0323h (pch = 03h, pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + ac c, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point ? ? 2.1.7 h, l registers the h and l registers are the 8-bit buffers. there are two major functions of these registers. z can be used as general working registers z can be used as ram data pointers with @hl register 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset x x x x x x x x 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset x x x x x x x x example: if want to read a data from ram address 20 h of bank_0, it can use indirectly addressing mode to
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 32 preliminary version 0.4 access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc example: clear general-purpose data memory area of bank 0 using @hl register. clr h ; h = 0, bank 0 b0mov l, #07fh ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l ? 1, if l = 0, finish the routine jmp clr_hl_buf ; not zero clr @hl end_clr: ; end of clear general purpose data memory area of bank 0 ? ?
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 33 preliminary version 0.4 2.1.7.1 x registers x register is an 8-bit buffer. there ar e two major functions of the register. z can be used as general working registers z can be used as rom data pointer with the movc instruction for look-up table 085h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x xbit7 xbit6 xbit5 xbit4 xbit3 xbit2 xbit1 xbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 ? note: please refer to the ?look-up table description? about x regi ster look-up table application.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 34 preliminary version 0.4 2.1.7.2 y, z registers the y and z registers are the 8-bit buffers. there ar e three major functions of these registers. z can be used as general working registers z can be used as ram data pointers with @yz register z can be used as rom data pointer with the movc instruction for look-up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z ? 1, if z= 0, finish the routine jmp clr_yz_buf ; not zero clr @yz end_clr: ; end of clear general purpose data memory area of bank 0 ?
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 35 preliminary version 0.4 2.1.8 r registers r register is an 8-bit buffer. there ar e two major functions of the register. z can be used as working register z for store high-byte data of look-up table (movc instruction executed, the high- byte data of specified rom address will be stored in r register and the low-byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset - - - - - - - - ? note: please refer to the ?look-up table description? about r regi ster look-up table application.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 36 preliminary version 0.4 2.2 addressing mode ? immediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specific ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. ? example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. ? note: in immediate addressing mode application, th e specific ram must be 0x80~0x87 working register. ? directly addressing mode the directly addressing mode moves the cont ent of ram location in or out of acc. ? example: move 0x12 ram location data into acc. b0mov a, 12h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. ? indirectly addressing mode the indirectly addressing mode is to access the memory by the dat a pointer registers (h/l, y/z). example: indirectly addressing mode with @hl register b0mov h, #0 ; to clear h register to access ram bank 0. b0mov l, #12h ; to set an immediate data 12h into l register. b0mov a, @hl ; use data pointer @hl reads a data from ram location ; 012h into acc. example: indirectly addressing mode with @yz register b0mov y, #0 ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 37 preliminary version 0.4 2.3 stack operation 2.3.1 overview the stack buffer has 8-level. these buffers are designed to push and pop up program counter?s (pc) data when interrupt service routine and ?call? inst ruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stknl are the stack buffers to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 38 preliminary version 0.4 2.3.2 stack registers the stack pointer (stkp) is a 4-bit register to store t he address used to access the st ack buffer, 12-bit data memory (stknh and stknl) set aside for temp orary storage of stack addresses. the two stack operations are writing to the top of the stac k (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation increments each time. that makes the stkp always point to the top address of stack buffer and wr ite the last program counter val ue (pc) into the stack buffer. the program counter (pc) value is stored in the stack bu ffer before a call instruction ex ecuted or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in t he system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - stkpb3 stkpb2 stkpb1 stkpb0 read/write r/w - - - r/w r/w r/w r/w after reset 0 - - - 1 1 1 1 bit[3:0] stkpbn: stack pointer (n = 0 ~ 3) bit 7 gie: global interrupt control bit. 0 = disable. 1 = enable. please refer to the interrupt chapter. ? example: stack pointer (stkp) reset, we strongl y recommended to clear the stack pointers in the beginning of the program. mov a, #00001111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - - snpc11 snpc10 snpc9 snpc8 read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 39 preliminary version 0.4 2.3.3 stack operation example the two kinds of stack-save operations re fer to the stack pointer (stkp) and writ e the content of program counter (pc) to the stack buffer are call instructi on and interrupt service. under each conditi on, the stkp decreases and points to the next available stack location. the stack buffer stor es the program counter about the op-code address. the stack-save operation is as the following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 0 1 1 1 1 free free - 1 1 1 1 0 stk0h stk0l - 2 1 1 0 1 stk1h stk1l - 3 1 1 0 0 stk2h stk2l - 4 1 0 1 1 stk3h stk3l - 5 1 0 1 0 stk4h stk4l - 6 1 0 0 1 stk5h stk5l - 7 1 0 0 0 stk6h stk6l - 8 0 1 1 1 stk7h stk7l - > 8 0 1 1 0 - - stack over, error there are stack-restore operations correspond to each push operation to restore the prog ram counter (pc). the reti instruction uses for interrupt service routine. the ret inst ruction is for call instruction. when a pop operation occurs, the stkp is incremented and points to the next free stack loca tion. the stack buffer restores the last program counter (pc) to the program counter registers. the stac k-restore operation is as the following table. stkp register stack buffer stack level stkpb3 stkpb2 stkpb1 stkpb0 high byte low byte description 8 0 1 1 1 stk7h stk7l - 7 1 0 0 0 stk6h stk6l - 6 1 0 0 1 stk5h stk5l - 5 1 0 1 0 stk4h stk4l - 4 1 0 1 1 stk3h stk3l - 3 1 1 0 0 stk2h stk2l - 2 1 1 0 1 stk1h stk1l - 1 1 1 1 0 stk0h stk0l - 0 1 1 1 1 free free -
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 40 preliminary version 0.4 3 3 3 reset 3.1 overview the system would be reset in three conditions as following. z power on reset z watchdog reset z brown out reset z external reset when any reset condition occurs, all syst em registers keep initial status, progra m stops and program counter is cleared. after reset status released, the system boots up and progra m starts to execute from org 0. the nt0, npd flags indicate system reset status. the system can depend on nt0, npd status and go to diffe rent paths by program. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd - - - c dc z read/write r/w r/w - - - r/w r/w r/w after reset - - - - - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd condition description 0 0 reserved -. 0 1 watchdog reset watchdog timer overflow. 1 0 power on reset and lvd reset. power voltage is lower than lvd detecting level. 1 1 external reset external reset pin detect low level status. finishing any reset sequence needs some time. the system provides complete procedures to make the power on reset successful. for different oscillat or types, the reset time is different. that causes the vdd rise rate and start-up time of different oscillator is not fixed. rc ty pe oscillator?s start-up time is very shor t, but the crystal type is longer. under clie nt terminal application, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 41 preliminary version 0.4 3.2 power on reset the power on reset depend on lvd operation for most power- up situations. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. z power-up: system detects the power voltage up and waits for power stable. z external reset: system checks external reset pin status. if exter nal reset pin is not high level, the system keeps reset status and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condition, system works well and clears watchdog timer by program. under error condition, system is in unknown situation and watchdog can?t be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset, the system restarts and returns normal mode. watchdog reset sequence is as following. z watchdog timer status: system checks watchdog timer overflow stat us. if watchdog timer ov erflow occurs, the system is reset. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the ?watchdog timer? about watchdog timer detail information.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 42 preliminary version 0.4 3.4 brown out reset 3.4.1 brown out description the brown out reset is a power dropping condition. the powe r drops from normal voltage to low voltage by external factors (e.g. eft interference or extern al loading changed). the brown out reset would make the system not work well or executing program error. vdd vss v1 v2 v3 system work well area system work error area brown out reset diagram the power dropping might through the voltage range that ?s the system dead-band. the dead-band means the power range can?t offer the system minimum operation power re quirement. the above diagram is a typical brown out reset diagram. there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead-band. v1 doesn?t touch the below area and not effe ct the system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead-band includes some conditions. dc application: the power source of dc application is usually using battery . when low battery condition and mcu drive any loading, the power drops and keeps in dead-band. under the situat ion, the power won?t drop dee per and not touch the system reset voltage. that makes the system under dead-band. ac application: in ac power application, the dc power is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e. g. driving motor. the loading operating induces noise and overlaps with the dc power. vdd drop s by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects the power on successful, but the power do wn situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead-band for a while.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 43 preliminary version 0.4 3.4.2 the system operating voltage decsription to improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. differe nt system executing rates have differe nt system minimum operating voltage. the electrical characteristic section shows the system voltage to executing rate relationship. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area normally the system operation voltage ar ea is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. the dead-band definition is the system minimum operat ing voltage above the system reset voltage. 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset as following. z lvd reset z watchdog reset z reduce the system executing rate z external reset circuit. (zener diode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the ? zener diode reset circuit?, ?voltage bias reset circuit? and ?external reset ic? can completely improve the brown out reset, dc low battery and ac slow power down conditions. 2. for ac power application and enhance eft performance, the s y stem clock is 4mhz/4 ( 1 mips ) and use external reset (? zener diode reset circui t?, ?voltage bias reset circuit?, ?external reset ic?). the structure can improve noise effective and get good eft characteristic.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 44 preliminary version 0.4 lvd reset: vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset. the lvd (low voltage detector) is built-in sonix 8-bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be triggered, an d the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of volt age and not easy to cover all dead-band range. using lvd to improve brown out reset is depend on application requiremen t and environment. if the power variation is very deep, violent and trigger the lvd, the lvd ca n be the protection. if the power variation can touch the lvd detect level and make system work error, the lvd can? t be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog timer in several addresses. the system executes normally and the watchdog won?t reset system. when the system is under dea d-band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously counti ng until overflow occurrence. the overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead-band, the system reset sequence won?t be successful and the system stays in reset status until the power return to normal range. reduce the system executing rate: if the system rate is fast and the dead-band exists, to redu ce the system executing rate can improve the dead-band. the lower system rate is with lower minimum operating voltage. select the power voltage that?s no dead-band issue and find out the mapping system rate. adjust the system ra te to the value and the syst em exits the dead-band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out rese t and is the complete solution. there are three external reset circuits to improve brown out reset including ?zener di ode reset circuit?, ?voltage bias reset circuit? and ?external reset ic?. these three reset structures use external rese t signal and control to make sure the mcu be reset under power dropping and under dead-band. the external rese t information is described in the next section.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 45 preliminary version 0.4 3.5 external reset external reset pin is schmitt trigger structure and low leve l active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the sy stem is reset. the external reset operation actives in power on and normal running mode. during system power-up, the ex ternal reset pin must be high level input, or the system keeps in reset status. exter nal reset sequence is as following. z external reset: system checks external reset pin status. if exter nal reset pin is not high level, the system keeps reset status and waits external reset pin released. z system initialization: all system registers is set as initia l conditions and system is ready. z oscillator warm up: oscillator operation is successfully and supply to system clock. z program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in ac power application? 3.6 external reset circuit 3.6.1 simply rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising signal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a power on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 46 preliminary version 0.4 3.6.2 diode & rc reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm this is the better reset circuit. the r1 and c1 circuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual po wer. the diode offers a power positive path to conduct higher power to vdd. it is can make reset pin voltage le vel to synchronize with v dd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of ?simply reset circ uit? and ?diode & rc reset circuit? is necessar y to limit any current flowing into reset pin from externa l capacitor c in the event of reset pin breakdown due to electrostatic discharge (esd) or electrical over-stress (eos). 3.6.3 zener diode reset circuit mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd vo ltage level is above ?vz + 0. 7v?, the c terminal of the pnp transistor outputs high voltage and mcu operates normal ly. when vdd is below ?vz + 0.7v?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification. select the right zene r voltage to conform the application.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 47 preliminary version 0.4 3.6.4 voltage bias reset circuit mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b the voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset ci rcuit. use r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to ?0.7v x (r1 + r2) / r1?, the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below ?0.7v x (r 1 + r2) / r1?, the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcu?s reset pin level varies with vdd voltage variation, and the differential voltage is 0.7v. if the vdd drops and the voltage lower than reset pin det ect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vd d and c terminal voltage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2 . for power consumption issue application, e.g. dc power system, the current must be considered to whole system power consumption. ? note: under unstable power condition as brown out re set, ?zener diode rest circuit? and ?volta g e bias reset circuit? can protects s y stem no an y error occurrence as power droppin g . when power drops below the reset detect volta g e, the s y stem reset would be tri gg ered, and then s y stem executes reset sequence. that makes sure the system work well under unstable power situation.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 48 preliminary version 0.4 3.6.5 external reset ic mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and good effect solution. by different application and system require ment to select suitable reset ic. the reset circuit can improve all power variation.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 49 preliminary version 0.4 4 4 4 system clock 4.1 overview the micro-controller is a dual clock sy stem. there are high-speed clock and low-speed clock. the high-speed clock is generated from the external oscillator circuit or on-chip 16mhz high-speed rc oscillator circuit (ihrc 16mhz). the low-speed clock is generated from lxin/lxout by 32768 crystal or rc oscillator circuit both the high-speed clock and the low-sp eed clock can be system clock (fosc). the system clock in slow mode is divided by 4 to be the instruction cycle (fcpu). ) normal mode (high clock): fcpu = fhosc / 4 , (fhosc= 4m/8m crystal) fcpu = fhosc / 16 , (fhosc=ihrc) ) slow mode (low clock): fcpu = flosc/4. 4.2 clock block diagram z hosc: high_clk code option. z fhosc: external high-speed clock / internal high-speed rc clock. z flosc: external low-speed clock . z fosc: system clock source. z fcpu: instruction cycle. fhosc. fcpu = fhosc/4 (fhosc=4m crystal) fcpu = fhosc/16 (fhosc=ihrc) flosc. fcpu = flosc/4 cpum[1:0] xin xout stphx hosc fosc fosc clkmd fcpu
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 50 preliminary version 0.4 4.3 oscm register the oscm register is an oscillator control regi ster. it controls oscillator status, system mode. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx 0 read/write r/w r/w r/ w r/w r/w r/w r/w - after reset 0 0 0 0 0 0 0 - bit 1 stphx: external high-speed os cillator control bit. 0 = external high-speed oscillator free run. 1 = external high-speed oscillator free run stop. internal low-speed rc oscillator is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = normal (dual) mode. syst em clock is high clock. 1 = slow mode. system clock is external low clock. bit[4:3] cpum[1:0]: cpu operating mode control bits. 00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved. bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v ? example: stop high-speed oscillator b0bset fstphx ; to stop exter nal high-speed oscillator only. ? example: when entering the power down mode (sl eep mode), both high-speed oscillator and internal low-speed oscillator will be stopped. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode).
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 51 preliminary version 0.4 4.4 system high clock the system high clock is from internal 16 mhz oscillator rc type or external oscilla tor. the high clock type is controlled by ?high_clk? code option. high_clk code option description ihrc_16m the high clock is internal 16mhz oscillator rc type. xin and xout pins are general purpose i/o pins. 4m the high clock is external oscilla tor. the typical frequency is 4mhz. 4.4.1 internal high rc the chip is built-in rc type internal high clock (16mhz) controlled by ?ihrc_1 6m? code options. in ?ihrc_16m? mode, the system clock is from internal 16mhz rc type oscillator and xin / xout pins are general-purpose i/o pins. z ihrc: high clock is internal 16mhz oscillator rc ty pe. xin/xout pins are general purpose i/o pins. 4.4.2 external high clock external high clock includes three modules (crystal/ceramic , rc and external clock signal). the high clock oscillator module is controlled by high_clk code option. the start up ti me of crystal/ceramic and rc type oscillator is different. rc type oscillator?s start-up time is very short, but the crystal?s is longer. the osci llator start-up time decides reset time length. 4mhz ceramic 4mhz crystal
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 52 preliminary version 0.4 4.4.2.1 crystal/ceramic crystal/ceramic devices are driven by xin, xout pins . for high/normal/low frequency, the driving currents are different. high_clk code option supports different frequencies. 12m option is for high speed (ex. 12mhz). 4m option is for normal speed (ex. 4mhz). mcu vcc gnd c 20pf xin x o u t vdd vss c 20pf crystal ? note: connect the crystal/ceramic and c as near as po ssible to the xin/xout/vss pins of micro-controller. 4.4.2.2 external clock signal selecting external clock signal input to be system clock is by rc option of high_clk code opt ion. the external clock signal is input from xin pin. xout pin is general purpose i/o pin. mcu vcc gnd vss vdd xin xout external clock input ? note: the gnd of exte rnal oscillator circuit must be as near as possible to vss pin of micro-controller.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 53 preliminary version 0.4 4.5 system low clock the system low clock source is the ex ternal low-speed oscillator. the low-sp eed oscillator can use 32768 crystal or rc type oscillator circuit. 4.5.1.1 crystal crystal devices are driven by lxin, lxout pins. the 32768 cr ystal and 10uf capacitor must be as near as possible to mcu. 4.5.1.2 rc type the external low clock supports watchdog clock sour ce and system slow mode controlled by clkmd. ) flosc = external low oscillator ) slow mode fcpu = flosc / 4 mcu vcc gnd c 10pf lxin l x o u t vdd vss c 10pf 32768hz mcu vcc gnd lxin l x o u t v d d vss c 22pf (3v) 35pf (5v)
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 54 preliminary version 0.4 in power down mode the external low clock will be stop. ? example: stop internal low-speed oscillator by power down mode. b0bset fcpum0 ; to stop external high- speed oscillator and in ternal low-speed ; oscillator called powe r down mode (sleep mode). ? note: the external low-speed clock can?t be turned off individually. it is controlled by cpum0, cpum1 bits of oscm register.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 55 preliminary version 0.4 4.5.2 system clock measurement under design period, the users can meas ure system clock speed by software instruction cycle (fcpu). this way is useful in rc mode. ? example: fcpu instruction cycl e of external oscillator. b0bset p0m.0 ; set p0.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p0.0 ; output fcpu toggle signal in low-sp eed clock mode. b0bclr p0.0 ; measure the fcpu frequency by oscilloscope. jmp @b ? note: do not measure the rc frequency directly from xin; the probe impendence will affect the rc frequency.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 56 preliminary version 0.4 5 5 5 system operation mode 5.1 overview the chip is featured with low power consumption by switching around four different modes as following. z normal mode (high-speed mode) z slow mode (low-speed mode) z power-down mode (sleep mode) z green mode power down mode (sleep mode) slow mode green mode normal mode clkmd = 1 clkmd = 0 p0, p1 wake-up function active. external reset circuit active. cpum1, cpum0 = 01. cpum1, cpum0 = 10. p0, p1 wake-up function active. t0 timer time out. external reset circuit active. p0, p1 wake-up function active. t0 timer time out. external reset circuit active. system mode switching diagram operating mode description mode normal slow green power down (sleep) remark ehosc running by stphx by stphx stop ext. lrc running running running stop cpu instruction executi ng executing stop stop t0 timer *active *active *active inactive * active if t0enb=1 tc0 timer *active *act ive *active inactive * active if tc0enb=1 tc1 timer *active *active inactive inactive * active if tc1enb=1 watchdog timer by watch_dog code option by watch_dog code option by watch_dog code option by watch_dog code option refer to code option description internal interrupt all active a ll active t0, tc0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0, tc0 reset p0, p1, reset ehosc : external high clock ext. lrc : external low clock
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 57 preliminary version 0.4 5.2 system mode switching ? example: switch normal/slow mode to power down (sleep) mode. b0bset fcpum0 ; set cpum0 = 1. ? note: during the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. ? example: switch normal mode to slow mode. b0bset fclkmd ;to set clkmd = 1, change the system into slow mode b0bset fstphx ;to stop external high -speed oscillator for power saving. ? example: switch slow mode to normal mode ( the external high-speed oscillator is still running) b0bclr fclkmd ;to set clkmd = 0 ? example: switch slow mode to normal mode (the external high-speed oscillator stops) if external high clock stop and program want to switch back normal mode. it is necessary to delay at least 20ms for external clock stable. b0bclr fstphx ; turn on the external high-speed oscillator. b0mov z, #54 ; if vdd = 5v, internal rc=32khz (typical) will delay @@: decms z ; 0.125ms x 162 = 20.25ms for external clock stable jmp @b b0bclr fclkmd ; change the system back to the normal mode ? example: switch normal/slow mode to green mode. b0bset fcpum1 ; set cpum1 = 1. ? note: if t0/tc0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can wakeup the system backs to the previous operation mode.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 58 preliminary version 0.4 ? example: switch normal/slow mode to green mode and enable t0 wakeup function. ; set t0 timer wakeup function. b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial val ue = 74h (to set t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode b0bclr fcpum0 ;to set cpumx = 10 b0bset fcpum1 ? note: during the green mode with t0 wake-up func tion, the wakeup pins, reset pin and t0 can wakeup the system back to the last mode. t0 wake-up period is controlled by program and t0enb must be set.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 59 preliminary version 0.4 5.3 wakeup 5.3.1 overview under power down mode (sleep mode) or green mode, progra m doesn?t execute. the wakeup trigger can wake the system up to normal mode or slow mode. the wakeup trigger sources are external trigger (p0, p1 level change) and internal trigger (t0/tc0 timer overflow). z power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0, p1 level change) z green mode is waked up to last mode (normal mode or slow mode). the wakeup triggers are external trigger (p0, p1 level change) and internal trigger (t0/tc0 timer overflow). 5.3.2 wakeup time when the system is in power down mo de (sleep mode), the high clock oscilla tor stops. when wake d up from power down mode, mcu waits for 2048 exte rnal high-speed oscillator clocks as the wake up time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. ? note: wakeup from green mode is no wakeup time because the clock doesn?t stop in green mode. the value of the wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + high clock start-up time ? note: the high clock start-up time is depended on the vdd and o scillator type of high clock. ? example: in power down mode (sleep mode), the sy stem is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/fosc * 2048 = 0.512 ms (fosc = 4mhz) the total wakeup time = 0.512 ms + oscillator start-up time
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 60 preliminary version 0.4 5.3.3 p1w wakeup control register under power down mode (sleep mode) and green mode, the i/o ports with wakeup function are able to wake the system up to normal mode. the port 0 and port 1 have wake up function. port 0 wakeup function always enables, but the port 1 is controlled by the p1w register. 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w - - - - p13w p12w p11w p10w read/write - - - - w w w w after reset - - - - 0 0 0 0 bit[3:0] p10w~p13w: port 1 wakeup function control bits. 0 = disable p1n wakeup function. 1 = enable p1n wakeup function.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 61 preliminary version 0.4 6 6 6 interrupt 6.1 overview this mcu provides three interrupt source s, including three internal interrupts (t0/tc0/tc1) and two external interrupt (int0, int1). the external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. once interrupt service is executed, the gie bit in stkp register will clear to ?0? for stopping other interrupt request. on the contrast, when interrupt serv ice exits, the gie bit will se t to ?1? to accept the next interrupts? request. all of the interrupt reque st signals are stored in intrq register. ? note: the gie bit must enable during all interrupt operation. 6.2 inten interrupt enable register inten is the interrupt request control register including one internal interrupts, one exte rnal interrupts enable control bits. one of the register to be set ?1? is to enable the interrupt request function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. t he program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed. 0c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten - tc1ien tc0ien t0ien - - p01ien p00ien read/write - r/w r/w r/w - - r/w r/w after reset - 0 0 0 - - 0 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = disable int0 interrupt function. 1 = enable int0 interrupt function. bit 1 p01ien: external p0.1 interrupt (int1) control bit. 0 = disable int1 interrupt function. 1 = enable int1 interrupt function. bit 4 t0ien: t0 timer interrupt control bit. 0 = disable t0 interrupt function. 1 = enable t0 interrupt function. bit 5 tc0ien: tc0 timer interrupt control bit. 0 = disable tc0 interrupt function. 1 = enable tc0 interrupt function. inten interrupt enable register interrupt enable gating intrq 5-bit latchs p00irq p01irq interrupt vector address (0008h) global interrupt request signal int0 trigger t0 time out tc0 time out int1 trigger tc0 time out t0irq tc0irq tc1irq
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 62 preliminary version 0.4 bit 6 tc1ien: tc1 timer interrupt control bit. 0 = disable tc1 interrupt function. 1 = enable tc1 interrupt function.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 63 preliminary version 0.4 6.3 intrq interrupt request register intrq is the interrupt request flag register. the register incl udes all interrupt request indication flags. each one of the interrupt requests occurs, the bit of the intrq register would be set ?1?. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vect or of program, users know the any interrupt requests occurring by the register and do the routi ne corresponding of the interrupt request. 0c8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq - tc1irq tc0irq t0irq - - p01irq p00irq read/write - r/w r/w r/w - - r/w r/w after reset - 0 0 0 - - 0 0 bit 0 p00irq: external p0.0 interrupt (int0) request flag. 0 = none int0 interrupt request. 1 = int0 interrupt request. bit 1 p01irq: external p0.1 interrupt (int1) request flag. 0 = none int1 interrupt request. 1 = int1 interrupt request. bit 4 t0irq: t0 timer interrupt request flag. 0 = none t0 interrupt request. 1 = t0 interrupt request. bit 5 tc0irq: tc0 timer interrupt request flag. 0 = none tc0 interrupt request. 1 = tc0 interrupt request. bit 6 tc1irq: tc1 timer interrupt request flag. 0 = none tc1 interrupt request. 1 = tc1 interrupt request. 6.4 gie global interrupt operation gie is the global interrupt control bit. all interrupts start wo rk after the gie = 1 it is necessary for interrupt service request. one of the interrupt requests occurs, and the program co unter (pc) points to the interrupt vector (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global interrupt. 1 = enable global interrupt. ? example: set global interrupt control bit (gie). b0bset fgie ; enable gie
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 64 preliminary version 0.4 ? note: the gie bit must enable during all interrupt operation.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 65 preliminary version 0.4 6.5 push, pop routine when any interrupt occurs, system will jump to org 8 and ex ecute interrupt service routine. it is necessary to save acc, pflag data. the chip includes ?pus h?, ?pop? for in/out interrupt service routine. the two instruction only save working registers 0x80~0x87 including pflag data into buffers. the acc data must be saved by program. ? note: 1. ?push?, ?pop? instructions onl y process 0x80~0x87 working registers and pflag register. users have to save and load acc by program as interrupt occurrence. 2. the buffer of push/pop instruction is only one level and is independent to ram or stack area. ? example: store acc and paflg data by push, po p instructions when interrupt service routine executed. .data accbuf ds 1 ; accbuf is acc data buffer. .code org 0 jmp start org 8 jmp int_service org 10h start: ? int_service: b0xch a, accbuf ; save acc in a buffer push ; save 0x80~0x87 working registers and pflag register to buffers. ? ? pop ; load 0x80~0x87 working registers and pflag register from buffers. b0xch a, accbuf ; restore acc from buffer reti ; exit interrupt service vector ? endp
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 66 preliminary version 0.4 6.6 int0 (p0.0) interrupt operation when the int0 trigger occurs, the p00irq will be set to ?1 ? no matter the p00ien is enable or disable. if the p00ien = 1 and the trigger event p00irq is also set to be ?1?. as t he result, the system will execute the interrupt vector (org 8). if the p00ien = 0 and the trigger event p00irq is still se t to be ?1?. moreover, the sy stem won?t execute interrupt vector even when the p00irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation. ? note: the interrupt trigger direction of p0.0 is control by pedge register. 0bfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge pedgen - - p00g1 p00g0 - - - r/w - - r/w r/w - - - bit7 pedgen: interrupt and wakeup trigger edge control bit. 0 = disable edge trigger function. port 0: low-level wakeup trigger and falling edge interrupt trigger. port 1: low-level wakeup trigger. 1 = enable edge trigger function. p0.0: both wakeup and interrupt trigger are controlled by p00g1 and p00g0 bits. p0.1: wakeup trigger and interrupt trigger is level change (falling or rising edge). port 1: wakeup trigger is level change (falling or rising edge). bit[4:3] p00g[1:0]: port 0.0 edge select bits. 00 = reserved, 01 = falling edge, 10 = rising edge, 11 = rising/falling bi-direction. ? example: setup int0 interrupt request and bi-direction edge trigger. mov a, #98h b0mov pedge, a ; set int0 interr upt trigger as bi-direction edge. b0bset fp00ien ; enable int0 interrupt service b0bclr fp00irq ; clear int0 interrupt request flag b0bset fgie ; enable gie ? example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq ? ; int0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 67 preliminary version 0.4 6.7 int1 (p0.1) interrupt operation when the int1 trigger occurs, the p01irq will be set to ?1 ? no matter the p01ien is enable or disable. if the p01ien = 1 and the trigger event p01irq is also set to be ?1?. as t he result, the system will execute the interrupt vector (org 8). if the p01ien = 0 and the trigger event p01irq is still se t to be ?1?. moreover, the sy stem won?t execute interrupt vector even when the p01irq is set to be ?1?. users need to be cautious with the operation under multi-interrupt situation. ? note: the interrupt trigger direction of p0.1 is controlled by pedgen bit. ? example: int1 interrupt request setup. b0bset fp01ien ; enable int1 interrupt service b0bclr fp01irq ; clear int1 interrupt request flag b0bset fgie ; enable gie ? example: int1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 fp01irq ; check p01irq jmp exit_int ; p01irq = 0, exit interrupt vector b0bclr fp01irq ; reset p01irq ? ; int1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 68 preliminary version 0.4 6.8 t0 interrupt operation when the t0c counter occurs overflow, the t0irq will be se t to ?1? however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be ?1? a nd the system enter interrupt ve ctor. if the t0ien = 0, the trigger event will make the t0irq to be ?1? but the system will not enter interr upt vector. users need to care for the operation under multi-interrupt situation. ? example: t0 interrupt request setup. b0bclr ft0ien ; disable t0 interrupt service b0bclr ft0enb ; disable t0 timer mov a, #20h ; b0mov t0m, a ; set t0 clock = fcpu / 64 mov a, #74h ; set t0c initial value = 74h b0mov t0c, a ; set t0 interval = 10 ms b0bset ft0ien ; enable t0 interrupt service b0bclr ft0irq ; clear t0 interrupt request flag b0bset ft0enb ; enable t0 timer b0bset fgie ; enable gie example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #74h b0mov t0c, a ; reset t0c. ? ; t0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 69 preliminary version 0.4 6.9 tc0 interrupt operation when the tc0c counter overflows, the tc0irq will be set to ?1? no matter the tc0ien is enable or disable. if the tc0ien and the trigger event tc0irq is set to be ?1?. as t he result, the system will execute the interrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the tc0ien is set to be ?1?. users need to be cautio us with the operation under multi-interrupt situation. ? example: tc0 interrupt request setup. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, #74h ; set tc0c initial value = 74h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie ? example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, #74h b0mov tc0c, a ; reset tc0c. ? ; tc0 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 70 preliminary version 0.4 6.10 tc1 interrupt operation when the tc1c counter overflows, the tc1irq will be set to ?1? no matter the tc1ien is enable or disable. if the tc1ien and the trigger event tc1irq is set to be ?1?. as t he result, the system will execute the interrupt vector. if the tc1ien = 0, the trigger event tc1irq is still set to be ?1?. moreover, the system won?t execute interrupt vector even when the tc1ien is set to be ?1?. users need to be cautio us with the operation under multi-interrupt situation. example: tc1 interrupt request setup. b0bclr ftc1ien ; disable tc1 interrupt service b0bclr ftc1enb ; disable tc1 timer mov a, #20h ; b0mov tc1m, a ; set tc1 clock = fcpu / 64 mov a, #74h ; set tc1c initial value = 74h b0mov tc1c, a ; set tc1 interval = 10 ms b0bset ftc1ien ; enable tc1 interrupt service b0bclr ftc1irq ; clear tc1 interrupt request flag b0bset ftc1enb ; enable tc1 timer b0bset fgie ; enable gie example: tc1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. b0bts1 ftc1irq ; check tc1irq jmp exit_int ; tc1irq = 0, exit interrupt vector b0bclr ftc1irq ; reset tc1irq mov a, #74h b0mov tc1c, a ; reset tc1c. ? ; tc1 interrupt service routine ? exit_int: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 71 preliminary version 0.4 6.11 multi-interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi-interrupt request requires setting the priority of the interrupt requests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag ?1? doesn?t mean the syst em will execute the interrupt vector. in addition, which means the irq flags can be set ?1? by the events without enable the interrupt. once the event occurs, the irq will be logic ?1?. the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge p01irq p0.1 trigger controlled by pedge t0irq t0c overflow tc0irq tc0c overflow tc1irq tc1c overflow for multi-interrupt conditions, two things need to be taking care of. one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 72 preliminary version 0.4 ? example: check the interrupt request under multi-interrupt operation org 8 ; interrupt vector jmp int_service int_service: ? ; push routine to save acc and pflag to buffers. intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intp01chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intp01chk: ; check int1 interrupt request b0bts1 fp01ien ; check p01ien jmp intt0chk ; jump check to next interrupt b0bts0 fp01irq ; check p01irq jmp intp01 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; jump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp inttc1chk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; jump to tc0 interrupt service routine inttc1chk: ; check t1 interrupt request b0bts1 ftc1ien ; check tc1ien jmp int_exit ; jump check to next interrupt b0bts0 ftc1irq ; check tc1irq jmp inttc1 ; jump to tc1 interrupt service routine int_exit: ? ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 73 preliminary version 0.4 7 7 7 i/o port 7.1 i/o port mode the port direction is programmed by pnm register. all i/o ports can select input or output direction expects input mode only of port0. 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1m - - - - p13m p12m p11m p10m read/write - - - - r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 0c2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2m - - - - - - p21m p20m read/write - - - - - - r/w r/w after reset - - - - - - 0 0 0c4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4m - - - - - p42m p41m p40m read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0c5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5m - - - p54m p53m p52m p51m p50m read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~5). 0 = pn is input mode. 1 = pn is output mode. ? note: 1. users can program them by bit c ontrol instructions (b0bset, b0bclr). 2. port 0 is input only port 3. port 2 is shared with xin and xout ? example: i/o mode selecting clr p1m ; set all ports to be input mode. clr p2m mov a, #0ffh ; set all ports to be output mode. b0mov p1m,a b0mov p2m, a b0bclr p1m.0 ; set p1.0 to be input mode. b0bset p1m.0 ; set p1.0 to be output mode.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 74 preliminary version 0.4 7.2 i/o pull up register 0e0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0ur - - - - - - p01r p00r read/write - - - - - - w w after reset - - - - - - 0 0 0e1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1ur - - - - p13r p12r p11r p10r read/write - - - - w w w w after reset - - - - 0 0 0 0 0e2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2ur - - - - - - p21r p20r read/write - - - - - - w w after reset - - - - - - 0 0 0e4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4ur - - - - - p42r p41r p40r read/write - - - - - w w w after reset - - - - - 0 0 0 0e5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5ur - - - p54r p53r p52r p51r p50r read/write - - - w w w w w after reset - - - 0 0 0 0 0 ? note: pnur is write only register. ? example: i/o pull up register mov a, #0ffh ; enable port1 pull-up register, b0mov p1ur,a
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 75 preliminary version 0.4 7.3 i/o port data register 0d0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - - - - - p01 p00 read/write - - - - - - r/w r/w after reset - - - - - - 0 0 0d1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1 - - - - p13 p12 p11 p10 read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 0d2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p2 - - - - - - p21 p20 read/write - - - - - - r/w r/w after reset - - - - - - 0 0 0d4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4 - - - - - p42 p41 p40 read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 0d5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 - - - p54 p53 p52 p51 p50 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 ? example: read data from input port. b0mov a, p0 ; read data from port 0 b0mov a, p1 ; read data from port 1 b0mov a, p4 ; read data from port 4 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p1, a b0mov p2, a b0mov p4, a b0mov p5, a ? example: write one bit data to output port. b0bset p1.0 ; set p1.0 to be ?1?. b0bclr p1.0 ; set p1.0 to be ?0?.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 76 preliminary version 0.4 8 8 8 timers 8.1 watchdog timer (wdt) the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program goes into the unknown status by noise interferen ce, wdt overflow signal raises and resets mcu. the instruction that clears the watchdog timer (? b0bset fwdrst ?) s hould be executed within a certain per iod. if an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted. 0cah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm wtcks wdrst wdrate cpum1 cpum0 clkmd stphx 0 read/write r/w r/w r/ w r/w r/w r/w r/w - after reset 0 0 0 0 0 0 0 - bit5 wdrate: watchdog timer rate select bit. 0 = f cpu 2 14 1 = f cpu 2 8 bit6 wdrst: watchdog timer reset bit. 0 = no reset 1 = clear the watchdog timer?s counter. (the detail information is in watchdog timer chapter.) bit7 wtcks: watchdog clock source select bit. 0 = f cpu 1 = internal rc low clock. watchdog timer overflow table. wtcks wtrate clkmd watchdog timer overflow time 0 0 0 1 / ( fcpu 2 14 16 ) = 293 ms, fosc=3.58mhz 0 1 0 1 / ( fcpu 2 8 16 ) = 500 ms, fosc=32768hz 0 0 1 1 / ( fcpu 2 14 16 ) = 65.5s, fosc=16khz@3v 0 1 1 1 / ( fcpu 2 8 16 ) = 1s, fosc=16khz@3v 1 - - 1 / ( 16k 512 16 ) ~ 0.5s @3v ? note: the watchdog timer can be enabled or disabled by the code option.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 77 preliminary version 0.4 watchdog timer application note is as following. z before clearing watchdog timer, check i/o status and check ram contents c an improve system error. z don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. z clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example: an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: ? ; check i/o. ? ; check ram err: jmp $ ; i/o or ram error. program jump here and don?t ; clear watchdog. wait watchdog timer overflow to reset ic. correct: ; i/o and ram are correct. clear watchdog timer and ; execute program. b0bset fwdrst ; only one clearing watchdog timer of whole program. ? call sub1 call sub2 ? ? ? jmp main
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 78 preliminary version 0.4 8.2 timer 0 (t0) 8.2.1 overview the t0 is an 8-bit binary up timer and event counter. if t0 ti mer occurs an overflow (from ffh to 00h), it will continue counting and issue a time-out signal to trigger t0 interrupt to request interrupt service. the main purposes of the t0 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) rtc timer: generates interrupts at real time inte rvals based on the selected clock source. rtc function is only available in t0tb=1. ) green mode wakeup function: t0 can be green mode wake -up time as t0enb = 1. system will be wake-up by t0 time out. fcpu t0 rate (fcpu/2~fcpu/256) t0enb cpum0,1 t0c 8-bit binary up counting counter t0 time out load internal data bus t0enb rtc t0tb ? note: in rtc mode, the t0 interval time is fixed at 0.5 sec and isn?t controlled by t0c.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 79 preliminary version 0.4 8.2.2 t0m mode register 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc, t0 will be 0.5 sec rtc (low clock must be 32768 cyrstal). bit 1 tc0gn: enable tc0 green mode wake up function 0 = disable. 1 = enable. bit 2 tc0x8: tc0 internal clock source control bit. 0 = tc0 internal clock source is fcpu. tc0rate is from fcpu/2~fcpu/256. 1 = tc0 internal clock source is fo sc. tc0rate is from fosc/1~fosc/128. bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is from fcpu/2~fcpu/256. 1 = tc1 internal clock source is fo sc. tc1rate is from fosc/1~fosc/128. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. ? note: t0rate is not available in rtc mode. the t0 interval time is fixed at 0.5 sec.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 80 preliminary version 0.4 8.2.3 t0c counting register t0c is an 8-bit counter register for t0 interval time control. 0d9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * input clock) ? example: to set 10ms interval time for t0 interr upt. high clock is external 4mhz. fcpu=fosc/4. select t0rate=010 (fcpu/64). t0c initial value = 256 - (t0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of t0. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) t0rate t0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us ? note: t0c is not available in rtc mode. the t0 interval time is fixed at 0.5 sec.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 81 preliminary version 0.4 8.2.4 t0 timer operation sequence t0 timer operation sequence of setup t0 timer is as following. ) stop t0 timer counting, disable t0 interrupt function and clear t0 interrupt request flag. b0bclr ft0enb ; t0 timer. b0bclr ft0ien ; t0 interrupt function is disabled. b0bclr ft0irq ; t0 interrupt request flag is cleared. ) set t0 timer rate. mov a, #0xxx0000b ;the t0 rate control bi ts exist in bit4~bit6 of t0m. the ; value is from x000xxxxb~x111xxxxb. b0mov t0m,a ; t0 timer is disabled. ) set t0 clock source from fcpu or rtc. b0bclr ft0tb ; select t0 fcpu clock source. or b0bset ft0tb ; select t0 rtc clock source. ) set t0 interrupt interval time. mov a,#7fh b0mov t0c,a ; set t0c value. ) set t0 timer function mode. b0bset ft0ien ; enable t0 interrupt function. ) enable t0 timer. b0bset ft0enb ; enable t0 timer.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 82 preliminary version 0.4 8.3 timer/counter 0 (tc0) 8.3.1 overview the tc0 is an 8-bit binary up counting timer. tc0 has two cl ock sources including internal clock and external clock for counting a precision time. the internal clock source is from fcpu or fosc controlled by tc0x8 flag to get faster clock source (fosc). the external clock is int0 from p0.0 pi n (falling edge trigger). using tc0m register selects tc0c?s clock source from internal or external. if tc0 timer occu rs an overflow, it will continue counting and issue a time-out signal to trigger tc0 interrupt to request interrupt serv ice. tc0 overflow time is 0xff to 0x00 normally. under pwm mode, tc0 overflow is decided by pwm cycl e controlled by aload0 and tc0out bits. the main purposes of the tc0 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) external event counter: counts system ?events? based on falling edge detection of external clock signals at the int0 input pin. ) green mode wake-up function: tc0 can be green mode wake-up timer. system will be wake-up by tc0 time out. ) buzzer output ) pwm output fcpu tc0 rate (fcpu/2~fcpu/256) fosc tc0 rate (fosc/1~fosc/128) tc0x8 int0 (schmitter trigger) tc0cks tc0enb cpum0,1 tc0c 8-bit binary up counting counter tc0r reload data buffer compare aload0 r s tc0 time out auto. reload tc0 / 2 buzzer internal p5.4 i/o circuit p5.4 pwm pwm0out tc0out aload0, tc0out load
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 83 preliminary version 0.4 8.3.2 tc0m mode register 0dah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm0out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc0out, aload0 bits. bit 1 tc0out: tc0 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.4 is i/o function. 1 = enable, p5.4 is output tc0out signal. bit 2 aload0: auto-reload control bit. only valid when pwm0out = 0. 0 = disable tc0 auto-reload function. 1 = enable tc0 auto-reload function. bit 3 tc0cks: tc0 clock source select bit. 0 = internal clock (fcpu or fosc). 1 = external clock from p0.0/int0 pin. bit [6:4] tc0rate[2:0]: tc0 internal clock select bits. tc0rate [2:0] tc0x8 = 0 tc0x8 = 1 000 fcpu / 256 fosc / 128 001 fcpu / 128 fosc / 64 010 fcpu / 64 fosc / 32 011 fcpu / 32 fosc / 16 100 fcpu / 16 fosc / 8 101 fcpu / 8 fosc / 4 110 fcpu / 4 fosc / 2 111 fcpu / 2 fosc / 1 bit 7 tc0enb: tc0 counter control bit. 0 = disable tc0 timer. 1 = enable tc0 timer. ? note: when tc0cks=1, tc0 became an external event counter and tc0rate is useless. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0).
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 84 preliminary version 0.4 8.3.3 tc1x8, tc0x8, tc0gn flags 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc. bit 1 tc0gn: enable tc0 green mode wake up function 0 = disable. 1 = enable. bit 2 tc0x8: tc0 internal clock source control bit. 0 = tc0 internal clock source is fcpu. tc0rate is from fcpu/2~fcpu/256. 1 = tc0 internal clock source is fo sc. tc0rate is from fosc/1~fosc/128. bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is from fcpu/2~fcpu/256. 1 = tc1 internal clock source is fo sc. tc1rate is from fosc/1~fosc/128. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. ? note: under tc0 event counter mode (tc0ck s=1), tc0x8 bit and tc0rate are useless.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 85 preliminary version 0.4 8.3.4 tc0c counting register tc0c is an 8-bit counter register for tc0 interval time control. 0dbh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc0c initial value is as following. tc0c initial value = n - (tc0 interrupt interval time * input clock) n is tc0 overflow boundary number. tc0 timer overflow time has six types (tc0 timer, tc0 event counter, tc0 fcpu clock source, tc0 fosc clock source, pwm mode and no pw m mode). these parameters decide tc0 overflow time and valid value as follow table. tc0cks tc0x8 pwm0 aload0 tc0out n tc0c valid value tc0c value binary type remark 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 0 (fcpu/2~ fcpu/256) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 0 1 (fosc/1~ fosc/128) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 1 - - - - 256 0x00~0xff 00000000b~11111111b overflow per 256 count
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 86 preliminary version 0.4 ? example: to set 10ms interval time for tc0 interr upt. tc0 clock source is fcpu (tc0ks=0, tc0x8=0) and no pwm output (pwm0=0). high clock is external 4mhz . fcpu=fosc/4. select tc0rate=010 (fcpu/64). tc0c initial value = n - (tc0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of tc0, tc0x8 = 0. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us the basic timer table interval time of tc0, tc0x8 = 1. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) tc0rate tc0clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fosc/128 8.192 ms 32 us 1000 ms 7812.5 us 001 fosc/64 4.096 ms 16 us 500 ms 3906.25 us 010 fosc/32 2.048 ms 8 us 250 ms 1953.125 us 011 fosc/16 1.024 ms 4 us 125 ms 976.563 us 100 fosc/8 0.512 ms 2 us 62.5 ms 488.281 us 101 fosc/4 0.256 ms 1 us 31.25 ms 244.141 us 110 fosc/2 0.128 ms 0.5 us 15.625 ms 122.07 us 111 fosc/1 0.064 ms 0.25 us 7.813 ms 61.035 us
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 87 preliminary version 0.4 8.3.5 tc0r auto-load register tc0 timer is with auto-load function controlled by aload0 bit of tc0m. when tc0c overflow occurring, tc0r value will load to tc0c by system. it is easy to generate an ac curate time, and users don?t reset tc0c during interrupt service routine. ? note: under pwm mode, auto-load is enabled automatically. the aload0 bit is selecting overflow boundary. 0cdh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0r tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc0r initial value is as following. tc0r initial value = n - (tc0 interrupt interval time * input clock) n is tc0 overflow boundary number. tc0 timer overflow time has six types (tc0 timer, tc0 event counter, tc0 fcpu clock source, tc0 fosc clock source, pwm mode and no pw m mode). these parameters decide tc0 overflow time and valid value as follow table. tc0cks tc0x8 pwm0 aload0 tc0out n tc0r valid value tc0r value binary type 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 (fcpu/2~ fcpu/256) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 1 (fosc/1~ fosc/128) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - - 256 0x00~0xff 00000000b~11111111b ? example: to set 10ms interval time for tc0 interr upt. tc0 clock source is fcpu (tc0ks=0, tc0x8=0) and no pwm output (pwm0=0). high clock is external 4mhz . fcpu=fosc/4. select tc0rate=010 (fcpu/64). tc0r initial value = n - (tc0 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 88 preliminary version 0.4 8.3.6 tc0 clock freque ncy output (buzzer) buzzer output (tc0out) is from tc0 timer/counter frequen cy output function. by setting the tc0 clock frequency, the clock signal is output to p5.4 and the p5.4 general purpose i/o function is auto-disable. the tc0out frequency is divided by 2 from tc0 interval time. tc0out frequency is 1/2 tc0 frequency. the tc0 clock has many combinations and easily to make difference frequency. the tc0out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc0 overflow clock tc0out (buzzer) output clock ? example: setup tc0out output from tc0 to tc0out (p5.4). the external high-speed clock is 4mhz. the tc0out frequency is 0.5khz. because the tc0out signal is divided by 2, set the tc0 clock to 1khz. the tc0 clock source is from external o scillator clock. t0c rate is fcpu/ 4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 131. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc0c,a b0mov tc0r,a b0bset ftc0out ; enable tc0 output to p5.4 and disable p5.4 i/o function b0bset faload1 ; enable tc0 auto-reload function b0bset ftc0enb ; enable tc0 timer ? note: buzzer output is enable, and ?pwm0out? must be ?0?.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 89 preliminary version 0.4 8.3.7 tc0 timer operation sequence tc0 timer operation includes timer interrupt, event counter , tc0out and pwm. the sequence of setup tc0 timer is as following. ) stop tc0 timer counting, disable tc0 interrupt function and clear tc0 interrupt request flag. b0bclr ftc0enb ; tc0 timer, tc0out and pwm stop. b0bclr ftc0ien ; tc0 inte rrupt function is disabled. b0bclr ftc0irq ; tc0 interrupt request flag is cleared. ) set tc0 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc0 rate control bi ts exist in bit4~bit6 of tc0m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc0m,a ; tc0 interr upt function is disabled. ) set tc0 timer clock source. ; select tc0 internal / external clock source. b0bclr ftc0cks ; select tc0 internal clock source. or b0bset ftc0cks ; select tc 0 external clock source. ; select tc0 fcpu / fosc internal clock source . b0bclr ftc0x8 ; select tc0 fcpu internal clock source. or b0bset ftc0x8 ; select tc0 fosc internal clock source. ? note: tc0x8 is useless in tc0 external clock source mode. ) set tc0 timer auto-load mode. b0bclr faload0 ; enable tc0 auto reload function. or b0bset faload0 ; disable tc0 auto reload function. ) set tc0 interrupt interval time, tc0out (buzzer) frequency or pwm duty cycle. ; set tc0 interrupt interval time, tc 0out (buzzer) frequency or pwm duty. mov a,#7fh ; tc0c and tc0r value is decided by tc0 mode. b0mov tc0c,a ; set tc0c value. b0mov tc0r,a ; set tc0r value unde r auto reload mode or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload0 ; aload0, tc0out = 00, pwm cycle boundary is b0bclr ftc0out ; 0~255. or b0bclr faload0 ; aload0, tc0out = 01, pwm cycle boundary is b0bset ftc0out ; 0~63. or b0bset faload0 ; aload0, tc0out = 10, pwm cycle boundary is b0bclr ftc0out ; 0~31. or b0bset faload0 ; aload0, tc0out = 11, pwm cycle boundary is b0bset ftc0out ; 0~15.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 90 preliminary version 0.4 ) set tc0 timer function mode. b0bset ftc0ien ; enable tc0 interrupt function. or b0bset ftc0out ; enable tc 0out (buzzer) function. or b0bset fpwm0out ; enable pwm function. or b0bset ftc0gn ; enable tc0 gre en mode wake-up function. ) enable tc0 timer. b0bset ftc0enb ; enable tc0 timer.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 91 preliminary version 0.4 8.4 timer/counter 1 (tc1) 8.4.1 overview the tc1 is an 8-bit binary up counting timer. tc1 has two cl ock sources including internal clock and external clock for counting a precision time. the internal clock source is from fcpu or fosc controlled by tc1x8 flag to get faster clock source (fosc). the external clock is int1 from p0.1 pi n (falling edge trigger). using tc1m register selects tc1c?s clock source from internal or external. if tc1 timer occu rs an overflow, it will continue counting and issue a time-out signal to trigger tc1 interrupt to request interrupt serv ice. tc1 overflow time is 0xff to 0x00 normally. under pwm mode, tc1 overflow is decided by pwm cycl e controlled by aload1 and tc1out bits. the main purpose of the tc1 timer is as following. ) 8-bit programmable up counting timer: generates interrupts at specific time intervals based on the selected clock frequency. ) external event counter: counts system ?events? based on falling edge detection of external clock signals at the int1 input pin. ) buzzer output ) pwm output fcpu tc1 rate (fcpu/2~fcpu/256) fosc tc1 rate (fosc/1~fosc/128) tc1x8 int1 (schmitter trigger) tc1cks tc1enb cpum0,1 tc1c 8-bit binary up counting counter tc1r reload data buffer compare aload1 r s tc1 time out auto. reload tc1 / 2 buzzer internal p5.3 i/o circuit p5.3 pwm pwm1out tc1out aload1, tc1out load
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 92 preliminary version 0.4 8.4.2 tc1m mode register 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1m tc1enb tc1rate2 tc1rate1 tc1rate0 tc1cks aload1 tc1out pwm1out read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm1out: pwm output control bit. 0 = disable pwm output. 1 = enable pwm output. pwm duty controlled by tc1out, aload1 bits. bit 1 tc1out: tc1 time out toggle signal output control bit. only valid when pwm1out = 0. 0 = disable, p5.3 is i/o function. 1 = enable, p5.3 is output tc1out signal. bit 2 aload1: auto-reload control bit. only valid when pwm1out = 0. 0 = disable tc1 auto-reload function. 1 = enable tc1 auto-reload function. bit 3 tc1cks: tc1 clock source select bit. 0 = internal clock (fcpu or fosc). 1 = external clock from p0.1/int1 pin. bit [6:4] tc1rate[2:0]: tc1 internal clock select bits. tc1rate [2:0] tc1x8 = 0 tc1x8 = 1 000 fcpu / 256 fosc / 128 001 fcpu / 128 fosc / 64 010 fcpu / 64 fosc / 32 011 fcpu / 32 fosc / 16 100 fcpu / 16 fosc / 8 101 fcpu / 8 fosc / 4 110 fcpu / 4 fosc / 2 111 fcpu / 2 fosc / 1 bit 7 tc1enb: tc1 counter control bit. 0 = disable tc1 timer. 1 = enable tc1 timer. ? note: when tc1cks=1, tc1 became an external event counter and tc1rate is useless. no more p0.1 interrupt request will be raised. (p0.1irq will be always 0).
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 93 preliminary version 0.4 8.4.3 tc1x8, tc0x8, tc0gn flags 0d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 tc1x8 tc0x8 tc0gn t0tb read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc. bit 1 tc0gn: enable tc0 green mode wake up function 0 = disable. 1 = enable. bit 2 tc0x8: tc0 internal clock source control bit. 0 = tc0 internal clock source is fcpu. tc0rate is from fcpu/2~fcpu/256. 1 = tc0 internal clock source is fo sc. tc0rate is from fosc/1~fosc/128. bit 3 tc1x8: tc1 internal clock source control bit. 0 = tc1 internal clock source is fcpu. tc1rate is from fcpu/2~fcpu/256. 1 = tc1 internal clock source is fo sc. tc1rate is from fosc/1~fosc/128. bit [6:4] t0rate[2:0]: t0 internal clock select bits. 000 = fcpu/256. 001 = fcpu/128. ? 110 = fcpu/4. 111 = fcpu/2. bit 7 t0enb: t0 counter control bit. 0 = disable t0 timer. 1 = enable t0 timer. ? note: under tc1 event counter mode (tc1ck s=1), tc1x8 bit and tc1rate are useless.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 94 preliminary version 0.4 8.4.4 tc1c counting register tc1c is an 8-bit counter register for tc1 interval time control. 0ddh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1c tc1c7 tc1c6 tc1c5 tc1c4 tc1c3 tc1c2 tc1c1 tc1c0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of tc1c initial value is as following. tc1c initial value = n - (tc1 interrupt interval time * input clock) n is tc1 overflow boundary number. tc1 timer overflow time has six types (tc1 timer, tc1 event counter, tc1 fcpu clock source, tc1 fosc clock source, pwm mode and no pw m mode). these parameters decide tc1 overflow time and valid value as follow table. tc1cks tc1x8 pwm1 aload1 tc1out n tc1c valid value tc1c value binary type remark 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 0 (fcpu/2~ fcpu/256) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 0 1 (fosc/1~ fosc/128) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 1 - - - - 256 0x00~0xff 00000000b~11111111b overflow per 256 count
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 95 preliminary version 0.4 ? example: to set 10ms interval time for tc1 interr upt. tc1 clock source is fcpu (tc1ks=0, tc1x8=0) and no pwm output (pwm1=0). high clock is external 4mhz . fcpu=fosc/4. select tc1rate=010 (fcpu/64). tc1c initial value = n - (tc1 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h the basic timer table interval time of tc1, tc1x1 = 0. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us the basic timer table interval time of tc1, tc1x8 = 1. high speed mode (fcpu = 4mhz / 4) low speed mode (fcpu = 32768hz / 4) tc1rate tc1clock max overflow interval one step = max/256 ma x overflow interval one step = max/256 000 fosc/128 8.192 ms 32 us 1000 ms 7812.5 us 001 fosc/64 4.096 ms 16 us 500 ms 3906.25 us 010 fosc/32 2.048 ms 8 us 250 ms 1953.125 us 011 fosc/16 1.024 ms 4 us 125 ms 976.563 us 100 fosc/8 0.512 ms 2 us 62.5 ms 488.281 us 101 fosc/4 0.256 ms 1 us 31.25 ms 244.141 us 110 fosc/2 0.128 ms 0.5 us 15.625 ms 122.07 us 111 fosc/1 0.064 ms 0.25 us 7.813 ms 61.035 us
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 96 preliminary version 0.4 8.4.5 tc1r auto-load register tc1 timer is with auto-load function controlled by aload1 bit of tc1m. when tc1c overflow occurring, tc1r value will load to tc1c by system. it is easy to generate an ac curate time, and users don?t reset tc1c during interrupt service routine. ? note: under pwm mode, auto-load is enabled automatically. the aload1 bit is selecting overflow boundary. 0deh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc1r tc1r7 tc1r6 tc1r5 tc1r4 tc1r3 tc1r2 tc1r1 tc1r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of tc1r initial value is as following. tc1r initial value = n - (tc1 interrupt interval time * input clock) n is tc1 overflow boundary number. tc1 timer overflow time has six types (tc1 timer, tc1 event counter, tc1 fcpu clock source, tc1 fosc clock source, pwm mode and no pw m mode). these parameters decide tc1 overflow time and valid value as follow table. tc1cks tc1x8 pwm1 aload1 tc1out n tc1r valid value tc1r value binary type 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 (fcpu/2~ fcpu/256) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 0 x x 256 0x00~0xff 00000000b~11111111b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 0 1 (fosc/1~ fosc/128) 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - - 256 0x00~0xff 00000000b~11111111b ? example: to set 10ms interval time for tc1 interr upt. tc1 clock source is fcpu (tc1ks=0, tc1x8=0) and no pwm output (pwm1=0). high clock is external 4mhz . fcpu=fosc/4. select tc1rate=010 (fcpu/64). tc1r initial value = n - (tc1 interrupt interval time * input clock) = 256 - (10ms * 4mhz / 4 / 64) = 256 - (10 -2 * 4 * 10 6 / 4 / 64) = 100 = 64h
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 97 preliminary version 0.4 8.4.6 tc1 clock freque ncy output (buzzer) buzzer output (tc1out) is from tc1 timer/counter frequen cy output function. by setting the tc1 clock frequency, the clock signal is output to p5.3 and the p5.3 general purpose i/o function is auto-disable. the tc1out frequency is divided by 2 from tc1 interval time. tc1out frequency is 1/2 tc1 frequency. the tc1 clock has many combinations and easily to make difference frequency. the tc1out frequency waveform is as following. 1 2 3 4 1 2 3 4 tc1 overflow clock tc1out (buzzer) output clock ? example: setup tc1out output from tc1 to tc1out (p5.3). the external high-speed clock is 4mhz. the tc1out frequency is 0.5khz. because the tc1out signal is divided by 2, set the tc1 clock to 1khz. the tc1 clock source is from external o scillator clock. tc1 rate is fcpu/ 4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 131. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#131 ; set the auto-reload reference value b0mov tc1c,a b0mov tc1r,a b0bset ftc1out ; enable tc1 output to p5.3 and disable p5.3 i/o function b0bset faload1 ; enable tc1 auto-reload function b0bset ftc1enb ; enable tc1 timer ? note: buzzer output is enable, and ?pwm1out? must be ?0?.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 98 preliminary version 0.4 8.4.7 tc1 timer operation sequence tc1 timer operation includes timer interrupt, event counter , tc1out and pwm. the sequence of setup tc1 timer is as following. ) stop tc1 timer counting, disable tc1 interrupt function and clear tc1 interrupt request flag. b0bclr ftc1enb ; tc1 timer, tc1out and pwm stop. b0bclr ftc1ien ; tc1 inte rrupt function is disabled. b0bclr ftc1irq ; tc1 interrupt request flag is cleared. ) set tc1 timer rate. (besides event counter mode.) mov a, #0xxx0000b ;the tc1 rate control bi ts exist in bit4~bit6 of tc1m. the ; value is from x000xxxxb~x111xxxxb. b0mov tc1m,a ; tc1 interr upt function is disabled. ) set tc1 timer clock source. ; select tc1 internal / external clock source. b0bclr ftc1cks ; select tc1 internal clock source. or b0bset ftc1cks ; select tc 1 external clock source. ; select tc1 fcpu / fosc internal clock source . b0bclr ftc1x8 ; select tc1 fcpu internal clock source. or b0bset ftc1x8 ; select tc1 fosc internal clock source. ? note: tc1x8 is useless in tc1 external clock source mode. ) set tc1 timer auto-load mode. b0bclr faload1 ; enable tc1 auto reload function. or b0bset faload1 ; disable tc1 auto reload function. ) set tc1 interrupt interval time, tc1out (buzzer) frequency or pwm duty cycle. ; set tc1 interrupt interval time, tc 1out (buzzer) frequency or pwm duty. mov a,#7fh ; tc1c and tc1r value is decided by tc1 mode. b0mov tc1c,a ; set tc1c value. b0mov tc1r,a ; set tc1r value unde r auto reload mode or pwm mode. ; in pwm mode, set pwm cycle. b0bclr faload1 ; aload1, tc1out = 00, pwm cycle boundary is b0bclr ftc1out ; 0~255. or b0bclr faload1 ; aload1, tc1out = 01, pwm cycle boundary is b0bset ftc1out ; 0~63. or b0bset faload1 ; aload1, tc1out = 10, pwm cycle boundary is b0bclr ftc1out ; 0~31. or b0bset faload1 ; aload1, tc1out = 11, pwm cycle boundary is b0bset ftc1out ; 0~15.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 99 preliminary version 0.4 ) set tc0 timer function mode. b0bset ftc1ien ; enable tc1 interrupt function. or b0bset ftc1out ; enable tc 1out (buzzer) function. or b0bset fpwm1out ; enable pwm function. ) enable tc0 timer. b0bset ftc0enb ; enable tc1 timer.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 100 preliminary version 0.4 8.5 pwm0 mode 8.5.1 overview pwm function is generated by tc0 timer counter and output the pwm signal to pwm0out pin (p5.4). the 8-bit counter counts modulus 256 bits. the value of the 8-bit count er (tc0c) is compared to the contents of the reference register (tc0r). when the reference register value (tc0r) is equal to the counter value (tc0c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the ratio (duty) of the pwm0 output is tc0r/256. pwm duty range tc0c valid value tc0r valid bits value max. pwm frequency (fcpu = 4mhz) remark 0/256~255/256 0x00~0xff 0x00~0xff 7. 8125k overflow per 256 count the output duty of pwm is with different tc0r. duty range is from 0/256~255/256. tc0 clock tc0r=00h tc0r=01h tc0r=80h tc0r=ffh 0 1 128 254 255 0 1 128 254 255 low low low high high low high
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 101 preliminary version 0.4 8.5.2 tc0irq and pwm duty in pwm mode, the frequency of tc0irq is depended on pwm duty range. from following diagram, the tc0irq frequency is related with pwm duty. 8.5.3 pwm program example ? example: setup pwm0 output from tc0 to pwm0out (p5.4). the extern al high-speed oscillator clock is 4mhz. fcpu = fosc/4. the duty of pwm is 30/256. the pwm frequency is about 1khz. the pwm clock source is from external oscillator clock. tc0 rate is fcpu/4. the tc0rate2~tc0rate1 = 110. tc0c = tc0r = 30. mov a,#01100000b b0mov tc0m,a ; set the tc0 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc0c,a b0mov tc0r,a b0bset fpwm0out ; enable pwm0 output to p5.4 and disable p5.4 i/o function b0bset ftc0enb ; enable tc0 timer ? note: the tc0r is write-only register. don?t pr ocess them using incms, decms instructions. ? example: modify tc0r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc0r, a incms buf0 ; get the new tc0r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc0r, a ? note: the pwm can work with interrupt request. tc0 overflow, tc0irq = 1 0xff tc0c value 0x00 pwm0 output (duty range 0~255)
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 102 preliminary version 0.4 8.5.4 pwm0 duty changing notice in pwm mode, the system will compare tc0c and tc0r all the time. when tc0c SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 103 preliminary version 0.4 8.6 pwm1 mode 8.6.1 overview pwm function is generated by tc1 timer counter and output the pwm signal to pwm1out pin (p5.3). the 8-bit counter counts modulus 256 bits. the value of the 8-bit count er (tc1c) is compared to the contents of the reference register (tc1r). when the reference register value (tc1r) is equal to the counter value (tc1c), the pwm output goes low. when the counter reaches zero, the pwm output is forced high. the ratio (duty) of the pwm1 output is tc1r/256, pwm duty range tc1c valid value tc1r valid bits value max. pwm frequency (fcpu = 4mhz) remark 0/256~255/256 0x00~0xff 0x00~0xff 7. 8125k overflow per 256 count the output duty of pwm is with different tc1r. duty range is from 0/256~255/256. tc1 clock tc1r=00h tc1r=01h tc1r=80h tc1r=ffh 0 1 128 254 255 0 1 128 254 255 low low low high high low high
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 104 preliminary version 0.4 8.6.2 tc1irq and pwm duty in pwm mode, the frequency of tc1irq is depended on pwm duty range. from following diagram, the tc1irq frequency is related with pwm duty. 8.6.3 pwm program example ? example: setup pwm1 output from tc1 to pwm1out (p5.3). the extern al high-speed oscillator clock is 4mhz. fcpu = fosc/4. the duty of pwm is 30/256. the pwm frequency is about 1khz. the pwm clock source is from external oscillator clock. tc1 rate is fcpu/4. the tc1rate2~tc1rate1 = 110. tc1c = tc1r = 30. mov a,#01100000b b0mov tc1m,a ; set the tc1 rate to fcpu/4 mov a,#30 ; set the pwm duty to 30/256 b0mov tc1c,a b0mov tc1r,a b0bset fpwm1out ; enable pwm1 output to p5.3 and disable p5.3 i/o function b0bset ftc1enb ; enable tc1 timer ? note: the tc1r is write-only register. don?t pr ocess them using incms, decms instructions. ? example: modify tc1r registers? value. mov a, #30h ; input a number using b0mov instruction. b0mov tc1r, a incms buf0 ; get the new tc1r value from the buf0 buffer defined by nop ; programming. b0mov a, buf0 b0mov tc1r, a ? note: the pwm can work with interrupt request. tc1 overflow, tc1irq = 1 0xff tc1c value 0x00 pwm1 output (duty range 0~255)
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 105 preliminary version 0.4 8.6.4 pwm1 duty changing notice in pwm mode, the system will compare tc1c and tc1r all the time. when tc1c SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 106 preliminary version 0.4 9 9 9 lcd driver there are 4 common pins and 24 segment pins in the sn8p192 9. the lcd scan timing is 1/4 duty and 1/2 or 1/3 bias structure to yield 96 dots lcd driver. 9.1 lcdm1 register lcdm1 register initial value = 000x 00xx 089h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lcdm1 lcdref1 lcdref0 lcdbnk - lcdenb lcdbias - - r/w r/w r/w r/w - r/w r/w - - after reset 0 0 0 - 0 0 - - bit[7:6] lcdref[0,1]: : selective range of resistance fo r lcd bias voltage-division. 00 = 400k resistance 01 = 200k resistance 10 = 100k resistance 11 = 50k resistance bit5 lcdbnk: lcd blank control bit. 0 = normal display 1 = all of the lcd dots off. bit3 lcdenb: lcd driver enable control bit. 0 = disable 1 = enable. bit2 lcdbias: lcd bias selection bit 0 = lcd bias is 1/3 bias 1 = lcd bias is 1/2 bias 9.2 option register description option initial value = xxxx xxx0 088h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 option - - - - - - - rclk r/w - - - - - - - r/w after reset - - - - - - - 0 rclk: external low oscillator type control bit. 0 = crystal mode 1 = rc mode. ? note1: circuit diagram when rclk=0 ?external low clock sets as crystal mode.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 107 preliminary version 0.4 ? note2: circuit diagram when ?rclk=1? will enable external low clock sets as rc mode. ? connect the c as near as possible to the vss pin of micro-controller. the frequency of external low rc is decided by the capacitor value. adjust capacitor value to about 32khz frequency. ? lcd frame rate is supplied from external low clock and frame rate is 64hz (32768hz/512) 9.3 lcd timing lcd frame rate is always supplied from external low clock and frame rate is 64hz (32768hz/512) lcd drive waveform, 1/4 duty, 1/2 bias com0 com1 com2 com3 seg0 (1010b) seg0 (0101b) 1 frame 1 frame lcd clock vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd vlcd vss 1/2*vlcd off on off off off on on on vlcd vss 1/2*vlcd off off off off on on on on
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 108 preliminary version 0.4 lcd drive waveform, 1/4 duty, 1/3 bias vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd vlcd vss 1/3*vlcd 2/3*vlcd com0 com1 com2 com3 seg0 (1010b) seg0 (0101b) 1 frame 1 frame lcd clock off on off off off off off off off on on on on on on on
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 109 preliminary version 0.4 9.4 lcd ram location ram bank 15?s address vs. common/segment pin location bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 com0 com1 com2 com3 - - - - seg 0 00h.0 00h.1 00h.2 00h.3 - - - - seg 1 01h.0 01h.1 01h.2 01h.3 - - - - seg 2 02h.0 02h.1 02h.2 02h.3 - - - - seg 3 03h.0 03h.1 03h.2 03h.3 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - seg 23 17h.0 17h.1 17h.2 17h.3 - - - - ? example: enable lcd function. set the lcd control bit (lcdenb) and program lcd ram to display lcd panel. b0bset flcdenb ; lcd driver.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 110 preliminary version 0.4 9.5 lcd circuit SN8P1929 in the lcd electric circuit, builds in se lective resistance for voltage-division. user can add resistance between vlcd / v3 / v2 / v1 for more driving current. build in register can be selected in four resist or value, 400k, 200k, 100k, and 50k controlled by lcdref0 and lcdref1 of the option register v1, v2, v3 only available for dice form and lqfp80 package lcd drive waveform, 1/4 duty, 1/2 bias 00 1] : lcdref[0 when , 3 r 400k r 400k vlcd n consumptio current lcd = ? ? ? ? ? ? + = note: if used external resister, the lcd curre nt consumption from vlcd always existence, even under power down mode. note: v2=1/3*vlcd v3=2/3*vlcd r 0.1u 0.1u v3 v2 v1 v lcd lcdenb 50k 50k 100k 200k lcdref[0:1] 50k 50k 100k 200k 50k 50k 100k 200k SN8P1929 r r lcdbias=0 (open) lcdref[0:1] lcdref[0:1]
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 111 preliminary version 0.4 lcd drive waveform, 1/4 duty, 1/3 bias 00 1] : lcdref[0 when , 2 r 400k r 400k vlcd n consumptio current lcd = ? ? ? ? ? ? + = note: if used external resister, the lcd current consumption from vlcd alw ays existence, even under power down mode. note: v2=v3=2/3*vlcd r 0.1u v3 v2 v1 v lcd lcdenb 50k 50k 100k 200k lcdref1 50k 50k 100k 200k SN8P1929 r lcdbias=1 (close) lcdref[0:1] lcdref[0:1]
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 112 preliminary version 0.4 1 1 1 0 0 0 in system program rom 10.1 overview in-system-program rom (isp rom), provided user an easy way to storage data into read-only-memory. choice any rom address and executing rom prog ramming instruction ? romwrt and supply 12.5v voltage on vpp/rst pin, after programming time which controlled by romcnt , romdah/romdal data will be programmed into address romadrh/romadrl. 10.2 romadrh/romadrl register 0a0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 romadrh vppchk romadr14 romadr13 romadr12 romadr11 romadr10 romadr9 romadr8 read/write r r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0a1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 romadrl romadr7 romadr6 romadr5 romadr4 romadr3 romadr2 romadr1 romadr0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 vppchk: vpp pin programming voltage. check 0 = vpp?s voltage not reached 12. 5v. can?t program isp rom 1 = vpp?s voltage reached 12. 5v. can program isp rom ? note 2: using marco @b0bts1_fvppchk and @b 0bts0_fvppchk for checking vpp voltage status. romadr[14:0] : isp rom programming address. rom address which will be programmed 10.3 romdah/romadl registers 0a2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 romdah romda15 romda14 romda13 romda12 romda11 romda10 romda9 romda8 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0a3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 romdal romda7 romda6 romda5 romda4 romda3 romda2 romda1 romda0 read/write r/w r/w r/ w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 romda[15:0] : isp rom programming data rom data which want to programming into rom area..
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 113 preliminary version 0.4 10.4 romcnt registers and romwrt instruction 0a4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 romcnt romcnt7 romcnt6 romcnt5 romcnt4 romcnt3 romcnt2 romcnt1 romcnt0 read/write w w w w w w w w after reset - - - - - - - - bit[7:0] romcnt [7:0]: isp rom programming time counter the isp rom programming time was controlled by romcnt[7:0] programming will be (256-romcnt)*4/fcpu the suggestion programming is 1ms fcpu romcnt programming time 1mips 6 1ms when all setting was done, execute romwrt instruction to program data romd a[15:0] into address romadr[14:0] ? note1: please keep vdd=5v when accessing isp rom. ? note2: after access romwrt, at least 3 nop instruction delay is necessary.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 114 preliminary version 0.4 10.5 isp rom routine example ? example : ; reserved isp rom area as 0xffff org 0100h @caldata: dw 0xffff ???.. ???.. ; program data 0xaa55 into address @caldata mov a, #@caldata$l b0mov romadrl, a ;move low byte address to romadrl mov a, #@caldata$h b0mov romadrh, a ;move low byte address to romadrh mov a, #0x55 b0mov romdal, a ;move low byte data to romdal mov a, #0xaa b0mov romdah, a ;move low byte data to romadrh ;vpp voltage check @b0bts1_ fvppchk ;check vpp voltage is 12.5v or not jmp $-1 ;if vpp not reach 12.5v, keep waiting. ;set programming counter and accessing isp rom @rom_wrt: mov a,#6 ;set programming counter b0mov romcnt,a romwrt ;programming isp rom nop ;nop delay nop ;nop delay nop ;nop delay ;vpp voltage check ;set vpp as vdd voltage. @b0bts0_ fvppchk ;check vpp voltage is vdd or not jmp $-1 ;if vpp still reach 12.5v, keep waiting. ;check programmed data b0mov z, #@caldata$l b0mov y, #@caldata$h movc ;move isp rom data into a and r cmprs a,#0x55 jmp @wrt_err b0mov a, r cmprs a,#0xaa jmp @wrt_err ;check isp rom data correction. ???..
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 115 preliminary version 0.4 1 1 1 1 1 1 charge-pump, pgia and adc 11.1 overview the SN8P1929 has a built-in voltage charge-pump/regulat or (cpr) to support a stable voltage 3.8v from pin avddr and 3.0v/2.4v/1.5v from pin ave+ with maximum 10ma current driving capacity . this cpr provides stable voltage for internal circuits (pgia, a dc from avddr) and external sensor (load cell or thermistor from ave+). the SN8P1929 series also integrated ? analog-to-digital converters (adc) to achieve 16-bit performance and up to 62500-step resolution. the adc has three different input c hannel modes: (1) two fully differential inputs (2) one fully differential input and two single-ended input s (3) four single-ended inputs. this adc is optimized for measuring low-level unipolar or bipolar signals in weight scale and medical applications. a very low noise chopper-stabilized programmable gain instrumentation amplifier (pgia) with selectable gains of 1x, 12.5x , 50x, 100x, and 200x in the adc to accommodate these applications. 11.2 analog input following diagram illustrates a block diagram of the pgia and adc module. the front end consists of a multiplexer for input channel selection, a pgia (programm able gain instrumentation amplifier), and the ? adc modulator. to obtain maximum range of adc output, the adc maximum input signal voltage v (x+, x-) should be close to but can?t over the reference voltage v(r+, r-), choosing a suitable reference voltage and a suitable gain of pgia can reach this purpose. the relative control bits are rvs [1:0 ] bits (reference voltage selection) in adcm register and gs[2:0] bits (gain selection) in ampm register. block diagram of pgia/adc module ? note 1: the low pass filter (c x ) will filter out choppe r frequency of pgia. ? note 2: the recommend value of c x is 0.1 f . this capacitor needs to place as close chip as possible. pgia ? adc module ai1+ ai1- ai2+ ai2- ampcks ampm x- x+ c x adcks adm r+ r+ adcdb temperature sensor ao+ ao- r ao+ r ao-
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 116 preliminary version 0.4 11.3 voltage charge pump / regulator (cpr) SN8P1929 is built in a cpr, which can provide a stable 3.8v (pin avddr) and 3.0v/2.4v/1.5v (pin ave+) with maximum 10ma current driving capacity. register cpm can enable or disable cpr and controls cpr working mode, another register cpcks sets cpr working clock to 4khz. because the power of pgia and adc is come from avddr, turn on avddr (avddrenb = 1) first before enabling pgia and adc. the avddr vo ltage was regulated from avddcp. in addition, the cp will need at least 10ms for output voltage stabilization after set cprenb to high. 11.3.1 cpm-charge pump mode register 095h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpm acmenb avddrenb avenb avesel1 avesel0 cpauto cpon cprenb r/w r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit0: cprenb: charge pump / regulator function enable control bit. 0 = disable charge pump and regulator, 1 = enable charge pump and regular. bit1: cpon: change pump always on function control bit (cprenb must = ?1?) 0 = charge pump on / off controlled by bit cpauto. 1 = always turn on the charge pump regulator. bit2: cpauto: charge pump auto mode function control bit 0 = disable charge pump auto mode. 1 = enable charge pump auto mode. bit3,4 avesel[1:0]: ave+ voltage selection control bit. avesel1 avesel0 ave+ voltage 1 1 3.0v 1 0 2.4v 0 1 1.5v 0 0 reserved bit5: avenb: ave+ voltage output control bit. 0 = disable ave+ output voltage 1 = enable ave+ output voltage bit6: avddrenb: regulator (avddr) voltage enable control bit. 0 = disable regulator and avddr output voltage 3.8v 1 = enable regulator and avddr output voltage 3.8v bit7: acmenb: analog common mode (acm) voltage enable control bit. 0 = disable analog common mode and acm output voltage 1.2v 1 = enable analog common mode and acm output voltage 1.2v ? note1: 30ms delay is necessary for output vo ltage stabilization after set cprenb = ?1?. ? note2: all current consumptions from avddr and ave+ (including pgia and adc) will time 2, when charge pump was enabled. ? note3: before enable charge pump/regulator , mu st enable band gap reference (bgrenb=1) first. ? note4 before enable acm voltage, enable avddr voltage first. ? note5: before enable pgia and adc , must enable band gap refere nce (bgrenb=1), acm (acmenb=1) and avddr(avddrenb). ? note6: cpr can work in slow mode, but cpcks , ampcks register value must be reassigned .
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 117 preliminary version 0.4 bit cprenb, cpon, and cpauto are charge-pump working mo de control bit. by these three bits, charge-pump can be set as off, always on, or auto mode. cprenb cpon cpauto avddrenb charge-pump status regulator status avddr pgia, adc function 0 x x 0 off off 0v not available 1 0 0 1 off on see note1 see note1 1 0 1 1 auto mode on 3.8v available 1 1 0 1 always on on 3.8v available in auto mode, charge-pump on/off depended on vdd voltage. auto-mode description: cprenb cpon cpauto avddrenb vdd charge-pump status regulator status avddr output pgia, adc function >4.1v off on 3.8v available 1 0 1 1 Q 4.1v on on 3.8v available ? note 1: when charge-pump is off and regulator is on, vdd voltage must be higher than 4.1v to make sure avddr output voltage for pgia, and adc functions are working well. cprenb cpon cpauto avddrenb vdd charge-pump status regulator status avddr output pgia, adc function >4.1v off on 3.8v available 1 0 0 1 Q 4.1v off on vdd not available ? note 1: for normally application, set cp as auto mode (cpauto = 1) is strongly recommended. ? note 2: if vdd is higher than 5.0v, don?t set charge-pump as always on mode. ? note 3: band gap reference voltage must be enable first (fbrgenb), before following function accessing: (reference ampm register for detail information) (1) charge pump /regulator. (2) pgia function. (3) 16- bit adc function. (4) low battery detect function
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 118 preliminary version 0.4 11.3.2 cpcks-charge pump clock register 096h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpcks cpcks3 cpcks2 cpcks1 cpcks0 r/w w w w w after reset 0 0 0 0 cpcks [3:0] register sets the charge-pump working clock; t he suggestion charge-pump clock is 13k~15k hz.@ normal mode, 2k@slow mode charge-pump clock= fcpu / 4 / (2^cpcks[3:0]) refer to the following table for cpcks [3:0] register value setting in different fosc frequency. fosc cpcks3 cpcks2 cpcks1 cpcks0 32768hz 2m 3.58m 4m/ihrc 8m 0 0 0 0 2.048k 125k 223.75k 250k 500k 0 0 0 1 na 62.5k 111.88k 125k 250k 0 0 1 0 na 31.25k 55.94k 62.5k 125k 0 0 1 1 na 15.625k 27.97k 31.25k 62.5k 0 1 0 0 na 7.8125k 13.985k 15.625k 31.25k 0 1 0 1 na 3.90625k 6.99k 7.8125k 15.625k 0 1 1 0 na 1.953215k 3.495k 3.90625k 7.8125k 0 1 1 1 na 0.976k 1.75k 1.953215k 3.90625k 1 0 0 0 na 0.488k 0.875k 0.976k 1.953215k 1 0 0 1 na 0.244k 0.438k 0.488k 0.976k 1 0 1 0 na 0.122k 0.219k 0.244k 0.488k 1 0 1 1 na 0.61k 0.11k 0.122k 0.244k 1 1 0 0 na 0.3k 0.055k 0.061k 0.122k 1 1 0 1 na 0.15k 0.028k 0.03k 0.61k 1 1 1 0 na 0.075k 0.014k 0.015k 0.3k 1 1 1 1 na 0.037k 0.007k 0.008k 0.15k ? note1: when enable charge pump, set charge pump clock as ?1011? to avoid vdd dropped. ? note2: in general application, cp working clock is about 13k~15k hz in normal mode, 2k hz in slow mode (external low clock mode). ? note3: the faster of charge pump clock, ave+ can load more current. ? note4: in slow mode or green mode, set cpcks= 0x00 for avddr/ave+/acm can supply the max current.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 119 preliminary version 0.4 example: charge-pump setting (fosc = 4m x?tal) @cpreg_init: xb0bset fbgrenb ;enable band gap reference voltage. mov a, #00001011b xb0mov cpcks, a ; set cpcks as sl owest clock to void vdd dropping. mov a, #00011100b ; xb0mov cpm, a ; set ave+=3.0v ,cp as auto mode and disable avddr, ave+, acm voltage before enable charge pump @cp_enable: xb0bset fcprenb ; enable charge-pump call @wait_200ms ; delay 200ms for charge-pump stabilize mov a, #0000100b xb0mov cpcks, a ; set cpcks as 15.6k for 10ma current loading. call @wait_100ms ; delay 100ms for voltage stabilize @avddr_enable: xb0bset favddrenb ; enable avddr voltage=3.8v call @wait_10ms ; delay 10ms for avddr voltage stabilize @acm_enable: xb0bset facmenb ; enable acm voltage=1.2v call @wait_5ms ; delay 5ms for acm voltage stabilize @ave_enable: xb0bset favenb ; enable ave+ voltage=3.0v/2.4v/1.5v call @wait_10ms ; delay 10ms for ave+ voltage stabilize ? ? ? note1: the charge pump delay (200ms and 100ms) can avoid vdd drop when cr2032 batter y application. if vdd source came from aa or aaa dry battery, the delay time can be shorten to 50ms. ? note2: please refer the SN8P1929 ev_board manual for the detail xb0mov, xb0bset command.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 120 preliminary version 0.4 11.4 pgia -programmable gain instrumentation amplifier SN8P1929 includes a low noise chopper-stabilized programmabl e gain instrumentation amplifier (pgia) with selection gains of 1x, 12.5x, 50x, 100x, and 200x by register ampm. t he pgia also provides two types channel selection mode: (1) two fully differential input (2) one fully differential inpu t and two single-ended inputs (3) four single-ended inputs, it was defined by register ampchs. 11.4.1 ampm- amplifier mode register 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampm chpenb bgrenb fds1 fds0 gs2 gs1 gs0 ampenb r/w r/w r/w r/w r/ w r/w r/w r/w r/w after reset 0 0 0 0 1 1 1 0 bit0: ampenb: pgia function enable control bit. 0 = disable pgia function 1 = enable pgia function bit[3:1]: gs [2:0]: pgia gain selection control bit gs [2:0] pgia gain 000 12.5 001 50 010 100 011 200 100,101,110 reserved 111 1 ? note: when selected gain is 1x, pgia can be disabled (ampenb=0) for power saving. bit[5:4] fds [1:0]: chopper low frequency setting ? note:set fds[1:0] = ?11? for all applications. bit6: bgrenb: band gap reference voltage enable control bit. 0 = disable band gap reference voltage 1 = enable band gap reference voltage ? note1: band gap reference voltage must be enable (fbrgenb), before following function accessing 1. charge pump /regulator. 2. pgia function. 3. 16- bit adc function. 4. low battery detect function ? note2: pgia can?t work in slow mode, unless gain selection is 1x. bit7: chpenb: chopper clock enable control pin 0 = disable chopper clock- chopper clock set to high . 1 = enable chopper clock ? note: set chpenb=1 for all applications.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 121 preliminary version 0.4 11.4.2 ampcks- pgia clock selection 092h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampcks - - - - - ampcks1 ampcks1 ampcks0 r/w - - - - - w w w after reset - - - - - 0 0 0 bit[2:0] ampcks [2:0] register sets the pgia chopper working clock. the suggestion chopper clock is 1.95k hz.@ 4mhz, 1.74k @ 3.58mhz. pgia clock= fcpu / 32 / (2^ampcks) refer to the following table for ampcks [2:0] register value setting in different fosc frequency. high clock ampcks2 amcks1 ampcks0 2m 3.58m 4m/ihrc 8m 0 0 0 15.625k 27.968k 31.25k 62.5k 0 0 1 7.8125k 13.98k 15.625k 31.25k 0 1 0 3.90625k 6.99k 7.8125k 15.625k 0 1 1 1.953125k 3.49k 3.90625k 7.8125k 1 0 0 976hz 1.748k 1.953125k 3.90625k 1 0 1 488hz 874hz 976hz 1.953125k 1 1 0 244hz 437hz 488hz 976hz 1 1 1 122hz 218hz 244hz 488hz ? note: in general application, set pgia chopper work ing clock is ~2k hz, but set clock to 250hz when hi g h clock is 32768 crystal or in internal low clock mode.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 122 preliminary version 0.4 11.4.3 ampchs-pgia channel selection 091h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ampchs - - - - chs3 chs2 chs1 chs0 r/w - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 chs [3:0]: pgia channel selection chs [3:0] selected channel v (x+, x-) output input-signal type 0000 ai1+, ai1- v (ai1+, ai1-) pgia gain differential 0001 ai2+, ai2- v (ai2+, ai2-) pgia gain differential 0010 ai1+, acm v (ai1+, acm) pgia gain single-ended 0011 ai1-, acm v (ai1-, acm) pgia gain single-ended 0100 ai2+, acm v (ai2+, acm) pgia gain single-ended 0101 ai2-, acm v (ai2-, acm) pgia gain single-ended 0110 acm, acm v (acm, acm) pgia gain input-short 0111 reserved n/a n/a 1000 temperature sensor v (v ts , 0.8v) 1 n/a others reserved n/a n/a ? note 1: v (ai+, ai-) = (ai+ voltage - ai- voltage) ? note 2: v (ai-, acm) = (ai- voltage - acm voltage) ? note 3: the purpose of input-short mode is only for pgia offset testing. ? note 4: when cpr is disable or s y stem in stop mode, si g nal on analo g input pins must be zero ( ?0?v, including ai+, ai-, x+, x-, r+ and r-) or it w ill cause the current consum ption from these pins. ampchs[3:0]=?0000? ampchs[3:0]=?0010? ampchs[3:0]=?0011? ampchs[2:0]=?0110? pgia ai1+ ai1- adc x+ x- ref+ ref- pgia ai1+ adc x+ x- ref+ ref- acm pgia ai1- adc x+ x- ref+ ref- acm pgia adc x+ x- ref+ ref- acm
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 123 preliminary version 0.4 11.4.4 temperature sensor (ts) in applications, sensor characteristic might change in differ ent temperature also. to get the temperature information, SN8P1929 build in a temperature senor (ts) for temperatur e measurement. select the respective pgia channel to access the temperature sensor adc output. ampchs[3:0]=?1000? ? note1: when selected temperature sensor, pgia gain must set to 1x, or the result will be incorrect. ? note2: under this setting, x+ will be th e v(ts) voltage, and x- will be 0.8v. ? note3: the temperature sensor was j ust a reference data not real air temperature. for precision application, please use external thermister sensor. ? in 25c, v(ts) will be about 0.8v, and if te mperature rise 10c, v(ts) will decr ease about 15mv, if temperature drop 10c, v(ts) will increase about 15mv, example: temperature v(ts) v(ref+,ref-) adc output 15 0.815v 0.8v 16211 25 0.800v 0.8v 15625 35 0.785v 0.8v 15039 by adc output of v(ts), can get temperatur e information and compensation the syste. ? note1: the v ( ts ) volta g e and temperature curve of each chip mi g ht different. calibration in room temperature is necessary when application temperature sensor. ? note2: the typical temperature parameter of temperature sensor is 1.5mv/c. 1x adc x+ x- ref+ ref- avddr avss 0.4v ts
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 124 preliminary version 0.4 example: pgia setting (fosc = 4m x?tal) @cpreg_init: xb0bset fbgrenb ;enable band gap reference voltage. mov a, #00001011b xb0mov cpcks, a ; set cpcks as sl owest clock to void vdd dropping. mov a, #00011100b ; xb0mov cpm, a ; set ave+=3.0v ,cp as auto mode and disable avddr, ave+, acm voltage, before enable charge pump @cp_enable: xb0bset fcprenb ; enable charge-pump call @wait_200ms ; delay 200ms for charge-pump stabilize mov a, #0000100b xb0mov cpcks, a ; set cpcks as 15.6k for 10ma current loading. call @wait_100ms ; delay 100ms for voltage stabilize @avddr_enable: xb0bset favddrenb ; enable avddr voltage=3.8v call @wait_10ms ; delay 10ms for avddr voltage stabilize @acm_enable: xb0bset facmenb ; enable acm voltage=1.2v call @wait_5ms ; delay 5ms for acm voltage stabilize @ave_enable: xb0bset favenb ; enable ave+ voltage=3.0v/2.4v/1.5v call @wait_10ms ; delay 10ms for ave+ voltage stabilize @pgia_init: mov a, #11110110b xb0mov ampm, a ; enable band gap, set :fds=?11? ,chpenb=1, pgia gain=200 mov a, #00000100b xb0mov ampcks, a ; set ampcks = ?100? fo r pgia working clock = 1.9k @ 4m x?tal mov a, #00h xb0mov ampchs, a ; selected pgia differential input channel= ai1+, ai1- @pgia_enable: xb0bset fampenb ; enable pgia function ? ; v (x+, x-) output = v (ai1+, ai1-) x 200 ? note 1: enable charge-pump/regulator before pgia working ? note 2: please set pgia relative registers first, then enable pgia function bit.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 125 preliminary version 0.4 example: pgia channel change: @pgia_init: mov a, #11110110b xb0mov ampm, a ; enable band gap, set :fds=?11? ,chpenb=1, pgia gain=200 mov a, #00000100b xb0mov ampcks, a ; set ampcks = ?100? fo r pgia working clock = 1.9k @ 4m x?tal mov a, #00000000b xb0mov ampchs, a ; selected pgia differential input channel= ai1+, ai1- @pgia_enable: xb0bset fampenb ; enable pgia function ? ; v (x+, x-) output = v (ai1+, ai1-) x 200 @pgia_sensor: mov a, #11110111b ;don?t disable pgia when change pgia ch. xb0mov ampm, a ; enable band gap, se t fds=?11?, chpenb=1, pgia gain=200 mov a, #00000001b xb0mov ampchs, a ; selected pgia as differential channel. ? ; v (x+, x-) output = v(ai2+,ai2-) x 200 @pgia_ts: mov a, #11110001b ;don?t disable pgia when change pgia ch. xb0mov ampm, a ; enable band gap, se t fds=?11?, chpenb=1, pgia gain=1x mov a, #00001000b xb0mov ampchs, a ; selected pgia as temperature sensor ch. ? ; v (x+, x-) output = v (ts, 0.4) x 1.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 126 preliminary version 0.4 11.5 16-bit adc 11.5.1 adcm- adc mode register 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcm - - - - irvs rvs1 rvs0 adcenb r/w - - - - r/w r/w r/w r/w after reset - - - 0 0 0 0 0 bit0: adcenb: adc function control bit: 0 = disable 16-bit adc, 1 = enable 16-bit adc bit1: rvs 0 : adc reference voltage selection bit 0 = selection adc as normal operation from x+,x-. 1 = selection adc as vdd voltage detect bit2: rvs 1 : adc reference voltage selection bit 1 0 = selection adc reference voltage from external reference r+,r-. 1 = selection adc reference voltage from internal reference bit3: irvs: internal reference voltage selection. 0 = internal reference voltage v(ref+,ref-) is ave+/0.133 (when ave+=3.0v, v(ref+,ref-)=0.4v) 1 = internal reference voltage v(ref+,ref-) is ave+/0.266 (when ave+=3.0v, v(ref+,ref-)=0.8v) bit4: always set to ?0? ad reference voltage ad channel input irvs rvs1 rvs0 avesel[1:0] ref+ ref- adcin+ adcin- note x 0 0 - r+ r- external ref. voltage 0 1 0 11 (ave+=3.0v) 0.8v 0.4v v (x+, x-) < 0.4v 0 1 0 10 (ave+=2.4v) 0.64v 0.32v v (x+, x-) < 0.32v 1 1 0 11 (ave+=3.0v) 1.2v 0.4v v (x+, x-) < 0.8v 1 1 0 10 (ave+=2.4v) 0.96v 0.32v v (x+, x-) < 0.64v 1 1 0 01 (ave+=1.5v) 0.6v 0.2v x+ x- v (x+, x-) < 0.4v x 0 1 - r+ r- external ref. voltage 0 1 1 0.8v 0.4v 1 1 1 11 (ave+=3.0v) 1.2v 0.4v (iave+=3.0v) 0 1 1 0.64v 0.32v 1 1 1 10 (ave+=2.4v) 0.96v 0.32v vdd *3/16 vdd* 2/16 (ave+=2.4v) ? note1: the adc conversion data is combined with adcdh and adcdl register in 2?s compliment with sign bit numerical format, and bit adcb15 is the sign bit of adc data. refer to followin g formula to calculate adc conversion data value. ? note2: the internal reference volta g e is divided from ave+, so the volta g e will follow the chan g in g with ave+(3.0v/2.4v/1.5v) whic h selected by avesel[1:0].
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 127 preliminary version 0.4 31250 ) ( ) ( ) ( ) ( ) ( ) ( 31250 ) ( ) ( ) ( ) ( ) ( ) ( x ref ref adcin adcin iondata adcconvers adcin adcin x ref ref adcin adcin iondata adcconvers adcin adcin ? ? + ? ? + ? = ? ? < + ? ? + ? ? + + = ? ? > + ? note: the internal reference voltage are generated from ave+ voltage. external and internal reference circuit table: external ref. circuit rvs1=0 internal reference circuit rvs1=1, irvs=1, ave+=3.0v irvs=1, ave+=2.4v irvs=1, ave+=1.5v irvs=0,ave+=3.0v irvs=0,ave+=2.4v avss ave+ ref+=r+ ref- =r- avss 0.32v 0.64v ave+=2.4v ref+ ref- avss ave+=3.0v 1.2v 0.4v ref- ref+ avss ave+=2.4v 0.96v 0.32v ref- ref+ avss 0.6v 0.2v ref- ref+ ave+=1.5v avss 0.4v 0.8v ave+=3.0v ref+ ref-
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 128 preliminary version 0.4 adcm=#xxx0x00xb, v(ref+, ref-) = v(r+, r-), a dc reference voltage from external r+,r-. adcm=#xxx0110xb, v(ref+, ref-) = v(1. 2v, 0.4v)=0.8v (ave+=3.0v) adc re ference voltage from internal 1.2v and 0.4v. adcm=#xxx0010xb, v(ref+, ref-) = v(0. 8v, 0.4v)=0.4v (ave+=3 .0v), adc reference voltage from internal 0.8v and 0.4v. adcm=#xxx0111xb, v(ref+, ref-) = v(1. 2v, 0.4v)=0.8v (ave+=3 .0v), adc reference voltage from internal 1.2v and 0.4v, and adc output is voltage measurement result. pgia pgia adc x+ x- ref+ ref- 0.4v 1.2v avss vdd 3/16vdd 2/16vdd pgia pgia adc x+ x- ref+ ref- r- r+ pgia pgia adc x+ x- ref+ ref- 0.4v 0.8v pgia pgia adc x+ x- ref+ ref- 0.4v 1.2v
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 129 preliminary version 0.4 11.5.2 adcks- adc clock register 094h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcks adcks7 adcks6 adcks5 adcks4 adcks3 adcks2 adcks1 adcks0 r/w w w w w w w w w after reset 0 0 0 0 0 0 0 0 adcks [7:0] register sets the adc working clock, the suggestion adc clock is 100k hz. refer the following table for adcks [7:0] regist er value setting in different fosc frequency. adc clock= (fosc / (256-adcks [7:0]))/2 adcks [7:0] f osc adc working clock 246 4m (4m / 10)/2 = 200k 236 4m (4m / 20)/2 = 100k 243 4m (4m / 13)/2 = 154k 231 4m (4m / 25)/2 = 80k adcks [7:0] f osc adc working clock 236 8m (8m / 20)/2 = 200k 216 8m (8m / 40)/2 = 100k 231 8m (8m / 25)/2 = 160k 206 8m (8m / 50)/2 = 80k ? note: in general application, adc working clock is 100k hz.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 130 preliminary version 0.4 11.5.3 adcdl- adc low-byte data register 098h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdl adcb7 adcb6 adcb5 adcb4 adcb3 adcb2 adcb1 adcb0 r/w r r r r r r r r after reset 0 0 0 0 0 0 0 0 11.5.4 adcdh- adc high-byte data register 099h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adcdh adcb15 adcb14 adcb13 adcb12 adcb11 adcb10 adcb8 adcb9 r/w r r r r r r r r after reset 0 0 0 0 0 0 0 0 adcdl [7:0]: output low byte data of adc conversion word. adcdh [7:0]: output high byte data of adc conversion word. . ? note1: adcdl [7:0] and adcdh [7:0] are both read only registers. ? note2: the adc conversion data is combined wi th adcdh, adcdl in 2?s compliment with sign bit numerical format, and bit adcb15 is the sign bit of adc data. adcb15=0 means data is positive value, adcb15=1 means data is negative value. ? note3: the positive full-scale-output val ue of adc conversion is 0x7a12. ? note4: the negative full-scale-output value of adc conversion is 0x85ee, ? note5: because of the adc design limitation, the ad c linear range is +28125~-28125 (decimal). the max adc output must keep inside this range. adc conversion data (2?s compliment, hexadecimal) decimal value 0x7a12 31250 ? ? 0x4000 16384 ? ? 0x1000 4096 ? ? 0x0002 2 0x0001 1 0x0000 0 0xffff -1 0xfffe -2 ? ? 0xf000 -4096 ? ? 0xc000 -16384 ? ? 0x85ee -31250
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 131 preliminary version 0.4 11.5.5 dfm-adc digital filter mode register 097h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dfm - - - - - wrs0 - drdy - - - - - r/w - r/w after reset - - - - - 0 - 0 bit0: drdy: adc data ready bit. 1 = adc output (update) new conv ersion data to adcdh, adcdl. 0 = adcdh, adcdl conversi on data are not ready. bit2: wrs [1:0]: adc output word rate selection: output word rate wrs0 adc clock = 200k adc clock = 100k adc clock = 80k 0 50hz 25 hz 20 hz 1 25hz 12.5 hz 10 hz ? note 1: ac power 50 hz noise will be filt er out when output word rate = 25hz ? note 2: ac power 60 hz noise will be filt er out when output word rate = 20hz ? note 3: both ac power 50 hz and 60 hz noise w ill be filter out when output word rate = 10hz ? note 4: clear bit drdy a fter got adc data or this bit will keep high all the time. ? note 5: adjust adc clock (adcks) and bit wrs0 can get suitable adc output word rate.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 132 preliminary version 0.4 example: charge-pump, pgia and adc setting (fosc = 4m x?tal) @cpreg_init: xb0bset fbgrenb ;enable band gap reference voltage. mov a, #00001011b xb0mov cpcks, a ; set cpcks as sl owest clock to void vdd dropping. mov a, #00011100b ; xb0mov cpm, a ; set ave+=3.0v ,cp as auto mode and di sable avddr, ave+, acm voltage ,before enable charge pump @cp_enable: xb0bset fcprenb ; enable charge-pump call @wait_200ms ; delay 200ms for charge-pump stabilize mov a, #0000100b xb0mov cpcks, a ; set cpcks as 15.6k for 10ma current loading. call @wait_100ms ; delay 100ms for voltage stabilize @avddr_enable: xb0bset favddrenb ; enable avddr voltage=3.8v call @wait_10ms ; delay 10ms for avddr voltage stabilize @acm_enable: xb0bset facmenb ; enable acm voltage=1.2v call @wait_5ms ; delay 5ms for acm voltage stabilize @ave_enable: xb0bset favenb ; enable ave+ voltage=3.0v/1.5v call @wait_10ms ; delay 10ms for ave+ voltage stabilize @pgia_init: mov a, #11110110b xb0mov ampm, a ;enable band gap, set :fds=?11? ,chpenb=1 pgia gain=200 mov a, #00000100b xb0mov ampcks, a ; set ampcks = ?100? fo r pgia working clock = 1.9k @ 4m x?tal mov a, #00h xb0mov ampchs, a ; selected pgia differential input channel= ai1+, ai1- @pgia_enable: xb0bset fampenb ; enable pgia function ? ; v (x+, x-) output = v (ai1+, ai1-) x 200 @adc_init: mov a, #00000000b xb0mov adcm, a ; selection adc reference voltage = v(r+, r-) mov a, #0236 xb0mov adcks, a ; set adcks = 236 for adc working clock = 100k @ 4m x?tal mov a, #00h xb0mov dfm, a ; set adc as continuous mode and wrs0 = ?0? @adc_enable: ; adc conversion rate =25 hz xb0bset fadcenb ; enable adc function @adc_wait: xb0bts1 fdrdy ; check adc output new data or not jmp @adc_wait ; wait for bit drdy = 1 @adc_read: ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ?
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 133 preliminary version 0.4 ? note: please set adc relative registers first, than enable adc function bit. example: adc reference voltage changes: @adc_init: mov a, #00000000b xbmov adcm, a ; selection adc reference voltage = v(r+, r-) mov a, #0236 xb0mov adcks, a ; set adcks = 236 fo r adc working clock = 100k @ 4m x?tal mov a, #00h xb0mov dfm, a ; set adc as continuous mode and wrs0 = ?0? 25 hz @adc_enable: xb0bset fadcenb ; enable adc function @adc_wait: xb0bts1 fdrdy ; check adc output new data or not jmp @adc_wait ; wait for bit drdy = 1 @adc_read: ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ? ? @adc_rvs1: mov a, #00001101b ;don?t disable adc when change reference votlage xb0mov adcm, a ; selection adc reference voltage internal v(1.2v,0.4v) @@: xb0bts1 fdrdy ; check adc output new data or not jmp @b ; wait for bit drdy = 1 ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ? ? @adc_rvs2: mov a, #00001111b ;don?t disable adc when change reference votlage xbmov adcm, a ; selection adc as voltage measure. @@: xb0bts1 fdrdy ; check adc output new data or not jmp @b ; wait for bit drdy = 1 ; output adc conversion word xb0bclr fdrdy xb0mov a, adcdh b0mov data_h_buf, a ; move adc c onversion high byte to data buffer. xb0mov a, adcdl b0mov data_l_buf, a ; move adc c onversion low byte to data buffer. ?
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 134 preliminary version 0.4 11.5.6 lbtm : low battery detect register SN8P1929 provided two different way to measure power voltage. one is from adc reference voltage selection. it will be more precise but take more time and a little bit comp lex. the another way is using build in voltage comparator, divide power voltage and connect to p4.0, bit lbto will out put the p4.1 voltage higher or lower than acm(1.2v) 09ah bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lbtm - - - - - lbto p41io lbtenb r/w - - - - - r r/w r/w after reset - - - - - 0 0 0 bit0 lbtenb: low battery detect mode control bit. 0 = disable low battery detect function, 1 = enable low battery detect function bit1: p41io: port 4.1 input/lbt function control bit. 0 = set p41 as i/o port, 1 = set p41 as lbt function bit2: lbto: low battery detect output bit. 0 = p4.2/lbt voltage higher than acm (1.2v) 1 = p4.2/lbt voltage lower than acm (1.2v) there are two circuit connections for lb t application, one is using p4.0 and p4.1, which can avoid power consumption in sleep mode, the another is using p4.0 only. the second way will leak a small current in power down mode but can use p4.1 for input application. these two circuits are following: lbtenb=1, p41io=1 lbtenb=1, p41io=0 p5.1 as lbt function, no leakage current in sleep mode p4.1 as input port, leak current in sleep mode. low battery voltage r1 r2 lbto=1 2.4v 1m 1m vdd<2.4v 3.6v 1.33m 0.66m vdd<3.6v 4.8v 1.5m 0.5m vdd<4.8v ? note: get lbto=1 more 10 times in a raw ever y certain period, ex. 20 ms to make sure the low batter y signal is stable. comparator acm lbt vdd p4.2 p4.1 r1 r2 vss 0.1u comparator acm lbt vdd p4.2 r1 r2 vss 0.1u
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 135 preliminary version 0.4 11.5.7 analog setting and application the most applications of SN8P1929 were for dc measuremen t ex. weight scale, pressure measure. in different applications had each analog capacitor setting to avoi d vdd drop when charge pump enable or can save cost. following table indicate different applications setting wh ich mcu power source came from cr2032 battery, aa/aaa dry battery or external regulator resistance and capacitor table: ai+ ai- x+/x- r+/r- acm avddr ave+ avddcp c+/c- vdd (pin24) vdd (pin31) power type c ai+ c ai- c x c r c acm c avddr c ave+ c avddcp c c c avdd c dvdd cr2032 (2.4~3v) 0.1uf 0.1uf 0.1uf 0.1uf 1uf 1uf 2.2uf 10uf 1uf 10uf 0.1uf cr2032 ((4.4~6v)) 0.1uf 0.1uf 0.1uf 0.1uf 1uf 1uf 2.2uf no no 10uf 0.1uf aa/aaa bat.(2.4~3v) 0.1uf 0.1uf 0.1uf 0.1uf 1uf 1uf 4.7uf 10uf 1uf 10uf 0.1uf aa/aaa bat.(4.4~6v) 0.1uf 0.1uf 0.1uf 0.1uf 1uf 1uf 4.7uf no no 10uf 0.1uf external 5v reg. 0.1uf 0.1uf 0. 1uf 0.1uf 1uf 1uf 4.7uf no no 10uf 0.1uf ? note 1: when mcu source from cr2032 battery, the ave+ loading can?t over 3ma, for example the load cell resistance can?t over 1k. ? note 2: in aa/aaa batter y application, the ave+ can loadin g 10ma current, so that the load cell can be up to 330 ohm. ? note 3: if vdd alwa y s over 4.2v, set char g e pump as auto or disable mode so that char g e pump will disable and current consumption will not time 2 from avddr and ave+. capacitors of avddr and c+/c- can be removed and connect avddcp to vdd. ? note 1:the positive note of c avddcp connect to avddcp and negative note connect to vdd ? note2: the positive note of c acm connect to avddr and negative note connect to acm
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 136 preliminary version 0.4 vdd=2.4v~4.2v analog capacitor connection vdd=4.2v~5.5v analog capacitor connection delay time: charge pump enable delay power type step 1 cpcks=#00001011b step 2 cpcks=#00000100b enable acm enable avddr enable ave+ cr2032 (2.4~3v) 200ms 100ms 5ms 50ms 50ms cr2032 ((4.4~6v)) - - 5ms 50ms 50ms aa/aaa bat.(2.4~3v) 100ms 50ms 5ms 50ms 50ms aa/aaa bat.(4.4~6v) - - 5ms 50ms 50ms external 5v reg. - - 5ms 50ms 50ms ? note 1: in cr2032 application, please set enou gh delay time or the vdd will drop when char g e pump enable ? note 2: if vdd always over 4.2v, set charge pump as auto or disable mode to disable charge pump. ? note 3: in aa/aaa dry battery application, de lay time is shorter than cr2032 application. avddcp c avddcp vdd acm c acm avddr c+ c- c c avddr ave+ c ave+ c avddr avss avddcp vdd acm c acm avddr c+ c- avddr ave+ c ave+ c avddr nc nc avss
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 137 preliminary version 0.4 1 1 1 2 2 2 application circuit 12.1 scale (load cell) application circuit ? note : please refer 10.5.7 for capacitor setting. c+ vdd (pin24) c- vss xin xout 3.58m x'tal p0.0 p4.2 20pf 20pf r- r+ x - x+ ai- ai+ bridge type sensor ave+ com 0 seg 0 lcd com 1 ave+ p4.1 p4.0 com 2 com 3 seg 1 seg 17 vlcd vdd/avddr ave+ p5.4 p5.0 c ai+ 100 c ai- c x c r+ c r- c ave+ c avdd c c avddcp vdd seg 23 seg 22 avddr c avddr avss acm avddr c acm rst 10k 104 vdd (pin31) c dvdd lxout 32768 x'tal 20pf 20pf lxin p0.1 p1.0 p1.1 p1.2 p1.3
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 138 preliminary version 0.4 12.2 thermometer application circuit ? note : please refer 10.5.7 for capacitor setting. thermopile ave+ thermistor acm acm 0.1uf 0.1uf c+ vdd (pin24) c- vss xin xout 3.58m x'tal p0.0 p4.2 20pf 20pf r- r+ x - x+ ai- ai+ com 0 seg 0 lcd com 1 ave+ p4.1 p4.0 com 2 com 3 seg 1 seg 17 vlcd vdd/avddr ave+ p5.4 p5.0 100 c x c r+ c r- c ave+ c avdd c c avddcp vdd seg 23 seg 22 avddr c avddr avss acm avddr c acm rst 10k 104 vdd (pin31) c dvdd lxout 32768 x'tal 20pf 20pf lxin p0.1 p1.0 p1.1 p1.2 p1.3
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 139 preliminary version 0.4 1 1 1 3 3 3 instruction table field mnemonic description c dc z cycle mov a,m a m - - 1 m mov m,a m a - - - 1 o b0mov a,m a m (bnak 0) - - 1 v b0mov m,a m (bank 0) a - - - 1 e mov a,i a i - - - 1 b0mov m,i m i, (m = only for working registers r, y, z , rbank & pflag) - - - 1 xch a,m a m - - - 1 b0xch a,m a m (bank 0) - - - 1 movc r, a rom [y,z] - - - 2 adc a,m a a + m + c, if occur carry, then c=1, else c=0 1 a adc m,a m a + m + c, if occur carry, then c=1, else c=0 1 r add a,m a a + m, if occur carry, then c=1, else c=0 1 i add m,a m a + m, if occur carry, then c=1, else c=0 1 t b0add m,a m (bank 0) m (bank 0) + a, if occur carry, then c=1, else c=0 1 h add a,i a a + i, if occur carry, then c=1, else c=0 1 m sbc a,m a a - m - /c, if occur borrow, then c=0, else c=1 1 e sbc m,a m a - m - /c, if occur borrow, then c=0, else c=1 1 t sub a,m a a - m, if occur borrow, then c=0, else c=1 1 i sub m,a m a - m, if occur borrow, then c=0, else c=1 1 c sub a,i a a - i, if occur borrow, then c=0, else c=1 1 daa to adjust acc?s data format from hex to dec. - - 1 mul a,m r, a a * m, the lb of product stored in acc and hb stored in r register. zf affected by acc. - - 2 and a,m a a and m - - 1 l and m,a m a and m - - 1 o and a,i a a and i - - 1 g or a,m a a or m - - 1 i or m,a m a or m - - 1 c or a,i a a or i - - 1 xor a,m a a xor m - - 1 xor m,a m a xor m - - 1 xor a,i a a xor i - - 1 swap m a (b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) m(b7~b4, b3~b0) - - - 1 r rrc m a rrc m - - 1 o rrcm m m rrc m - - 1 c rlc m a rlc m - - 1 e rlcm m m rlc m - - 1 s clr m m 0 - - - 1 s bclr m.b m.b 0 - - - 1 bset m.b m.b 1 - - - 1 b0bclr m.b m(bank 0).b 0 - - - 1 b0bset m.b m(bank 0).b 1 - - - 1 cmprs a,i zf,c a - i, if a = i, then skip next instruction - 1 + s b cmprs a,m zf,c a ? m, if a = m, then skip next instruction - 1 + s r incs m a m + 1, if a = 0, then skip next instruction - - - 1 + s a incms m m m + 1, if m = 0, then skip next instruction - - - 1 + s n decs m a m - 1, if a = 0, then skip next instruction - - - 1 + s c decms m m m - 1, if m = 0, then skip next instruction - - - 1 + s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 rompages1/0, pc13~pc0 d - - - 2 call d stack pc15~pc0, pc15/14 rompages1/0, pc13~pc0 d - - - 2 m ret pc stack - - - 2 i reti pc stack, and to enable global interrupt - - - 2 s push to push working registers (080h~087h) into buffers - - - 1 c pop to pop working registers (080h~087h) from buffers 1 nop no operation - - - 1 note: 1. processing oscm register needs to add extra one cycle. 2. if branch condition is true then ?s = 1?, otherwise ?s = 0?.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 140 preliminary version 0.4 1 1 1 4 4 4 development tools 14.1 development tool version 14.1.1 ice (in circuit emulation) z sn8ice 1k: (s8kd-2) full function emulates SN8P1929 series ? sn8ice1k ice emulation notice ? operation voltage of ice: 3.0v~5.0v. ? recommend maximum emulation speed at 5v: 4 mips (e.g. 16mhz crystal and fcpu = fhosc/4). ? use SN8P1929 ev-kit to emulation analog function. ? note: s8ice2k doesn?t support SN8P1929 serial emulation. 14.1.2 otp writer z easy writer v1.0: otp programming is controlled by ice wit hout firmware upgrade suffers. please refer easy writer user manual for detailed information. z mp-ez writer v1.0: stand-alone operation to support SN8P1929 mass production ? note: writer 3.0 doesn?t support SN8P1929 otp programming. 14.1.3 ide (integrated development environment) sonix 8-bit mcu integrated development environment include assembler, ice debugger and otp writer software. z for sn8ice 1k: sn8ide 1.99v or later z for easy writer and mp-easy writer: sn8ide 1.99v or later z m2ide v1.0x doesn?t support SN8P1929.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 141 preliminary version 0.4 14.2 otp programming pin to transition board mapping 14.2.1 the pin assignment of easy and mp ez writer transition board socket: easy writer jp1/jp2 easy writer jp3 (mapping to 48-pin text tool) vss 2 1 vdd dip1 1 48 dip48 ce 4 3 clk/pgclk dip2 2 47 dip47 oe/shiftdat 6 5 pgm/otpclk dip3 3 46 dip46 d0 8 7 d1 dip4 4 45 dip45 d2 10 9 d3 dip5 5 44 dip44 d4 12 11 d5 dip6 6 43 dip43 d6 14 13 d7 dip7 7 42 dip42 vpp 16 15 vdd dip8 8 41 dip41 rst 18 17 hls dip9 9 40 dip40 alsb/pdb 20 19 - dip10 10 39 dip39 dip11 11 38 dip38 jp1 for mp transition board dip12 12 37 dip38 jp2 for writer v3.0 transition board dip13 13 36 dip36 dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 25 dip25 jp3 for mp transition board 14.2.2 the pin assignment of writer v3.0 transition board socket: gnd 2 1 vdd ce 4 3 clk oe 6 5 pgm d0 8 7 d1 d2 10 9 d3 d4 12 11 d5 d6 14 13 d7 vpp 16 15 vdd rst 18 17 hls 20 19 writer v3.0 jp1 pin assignment
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 142 preliminary version 0.4 14.2.3 SN8P1929 series programming pin mapping: otp programming pin of SN8P1929 series chip name SN8P1929 easy, mp-ez writer and writer v3.0 otp ic / jp3 pin assignment number pin number pin 1 vdd 3,20,27,50 vdd 2 gnd 14,22,45 vss 3 clk 38 p1.0 4 ce - - 5 pgm 39 p1.1 6 oe 40 p1.2 7 d1 - - 8 d0 - - 9 d3 - - 10 d2 - - 11 d5 - - 12 d4 - - 13 d7 - - 14 d6 - - 15 vdd 3,20,27,50 vdd 16 vpp 44 rst 17 hls - - 18 rst - - 19 - - - 20 alsb/pdb 41 p1.3
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 143 preliminary version 0.4 1 1 1 5 5 5 electrical characteristic 15.1 absolute maximum rating supply voltage (v dd )??????????????..????????????? - 0.3v ~ 6.0v input in voltage (v in )???????????..???.???????? v ss - 0.2v ~ v dd + 0.2v operating ambient temperature (t opr )??????????????????? 0 c ~ + 70 c storage ambient temperature (t stor )???????..???.???????? ?40 c ~ + 125 c 15.2 electrical characteristic (all of voltages refer to v ss , v dd = 5.0v,f osc = 4mhz,fcpu=1mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit operating voltage vdd normal mode, vpp = vdd 2.4 5.0 5.5 v ram data retention voltage vdr - 1.5 - v v dd rise rate v por v dd rise rate to ensure power-on reset 0.05 - - v/ms vil1 all input pins vss - 0.3vdd v input low voltage vil2 reset pin vss - 0.2vdd v vih1 all input pins 0.7vdd - vdd v input high voltage vih2 reset pin 0.9vdd - vdd v reset pin leakage current ilekg vin = vdd - - 5 ua vin = vss , vdd = 3v 100 200 300 k ? i/o port pull-up resistor rup vin = vss , vdd = 5v 50 100 180 k ? i/o port input leakage current ilekg pull-up resistor disable, vin = vdd - - 2 ua i/o port source current ioh vop = vdd - 0.5v 8 12 - ma sink current iol vop = vss + 0.5v 8 15 - intn trigger pulse width tint0 int0 ~ int1 interrupt request pulse width 2/fcpu - - cycle vdd= 5v 4mhz / ihrc - 2.2 4 ma idd1 normal mode (low power disable, analog parts off) vdd= 3v 4mhz / ihrc - 1 2 ma vdd= 5v 4mhz / ihrc - 1.8 4 ma idd2 normal mode (low power enable, analog parts off) vdd= 3v 4mhz / ihrc - 0.8 2 ma vdd= 5v 4mhz / ihrc - 3 5 ma idd3 normal mode (low power disable, analog parts on) vdd= 3v 4mhz / ihrc - 2.2 4.5 ma vdd= 5v 4mhz / ihrc - 2.5 5 ma idd4 normal mode (low power enable, analog parts on) vdd= 3v 4mhz / ihrc - 2.2 4 ma vdd= 5v ext.32768hz - 20 30 ua idd5 slow mode (stop high clock, lcd off, cpr off) vdd= 3v ext.32768hz - 8 20 ua vdd= 5v ext.32768hz - 30 50 ua idd6 slow mode (stop high clock, lcd on 200k, cpr off) vdd= 3v ext.32768hz - 15 30 ua vdd= 5v ext.32768hz - 300 600 ua idd7 slow mode (stop high clock, lcd on 200k, cpr on) vdd= 3v ext.32768hz - 250 500 ua vdd= 5v ext.32768hz - 10 20 ua idd8 by_cpum vdd= 3v ext.32768hz - 4 4 ua vdd= 5v ext.32768hz - 15 30 ua idd9 green mode *stop high clock *lcd off *cpr off internal_rc always on vdd= 3v ext.32768hz - 6 12 ua vdd= 5v ext.32768hz - 21 40 ua supply current idd10 green mode *stop high clock *lcd on 200k by_cpum vdd= 3v ext.32768hz - 10 20 ua
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 144 preliminary version 0.4 vdd= 5v ext.32768hz - 25 50 ua idd11 *cpr off internal_rc always on vdd= 3v ext.32768hz - 12 25 ua vdd= 5v ext.32768hz - 300 600 ua by_cpum vdd= 3v ext.32768hz - 250 500 ua vdd= 5v ext.32768hz - 300 300 ua idd12 green mode *stop high clock *lcd on 200k *cpr on internal_rc always on vdd= 3v ext.32768hz - 250 500 ua vdd= 5v - 1 5 ua idd13 sleep mode vdd= 3v - 0.7 5 ua 25 1.9 2.0 2.1 v lvd detect level v lvd internal por detect level 40 ~85 1.8 2.0 2.2 v internal high clock freq. f ihrc internal high rc oscillator frequency 16-0.5 % 16 16+0.5 % mhz *these parameters are for design reference, not tested. ? note: analog parts including charge pu mp regulator (cpr), pgia and adc.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 145 preliminary version 0.4 (all of voltages refer to vdd=3.8v f osc = 4mhz, ambient temperature is 25 c unless otherwise note.) parameter sym. description min. typ. max. unit analog to digital converter operating current i dd_adc run mode @ 3.8v 800 1000 ua power down current i pdn stop mode @ 3.8v 0.1 1 ua conversion rate f smp adcks: 200khz 25 sps r+, r- input range (external ref.) 0.4 2.0 v reference voltage input voltage vref r+, r- input range (internal ref.) 0.2 2.0 v differential non-linearity dnl adc range 28125 0.5 0.5 lsb integral non-linearity inl adc range 28125 1 4 lsb no missing code nmc adc range 28125 16 bit noise free code nfc adc range 28125 14 16 bit effective number of bits enob adc range 28125 14 16 bit adc input range v ain 0.4 2.0 v temperature sensor inaccuracy e ts inaccuracy range vs. real temp. 8 pgia current consumption i dd_pgia run mode @ 3.8v 300 500 ua power down current i pdn stop mode @ 3.8v 0.1 ua input offset voltage vos 25 50 uv bandwidth bw 100 hz pgia gain range (gain=200x) gr vdd = 3.8v 180 200 250 pgia input range vopin vdd = 3.8v 0.4 2 v pgia output range vopout vdd = 3.8v 0.4 2 v band gap reference (refer to acm) band gap reference voltage v bg 1.160 1.210 1.260 v reference voltage temperature coefficient t acm 50* ppm/ operating current i bg run mode @ 3.8v 50 100 ua charge pump regulator supply voltage v cps normal mode 2.4 5.5 v regulator output voltage avddr v avddr 3.7 3.8 3.9 v regulator output voltage ave+ v ave+ ave+ set as 3.0v 2.9 3.0 3.1 v analog common voltage v acm 1.15 1.21 1.27 v regulator output current capacity i va+ 10 ma quiescent current i qi 700 1400 ua v acm driving capacity i src 10 ua v acm sinking capacity i snk 1 ua ? note : when charge pump enable, current consumpt ion will be time 2 of adc, pgia, cpr and loadin g from ave+, avddr.
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 146 preliminary version 0.4 1 1 1 6 6 6 package information 16.1 lqfp 80 pin
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 147 preliminary version 0.4 1 1 1 7 7 7 marking definition 17.1 introduction there are many different types in sonix 8-bit mcu production line. this note listed the produ ction definition of all 8-bit mcu for order or obtain information. this definition is only for blank otp mcu. 17.2 marking indetification system title sonix 8-bit mcu production rom type p=otp material b = pb-free package g = green package temperature range - = 0 ~ 70 d = -40 ~ 85 shipping package w = wafer h = dice q = lqfp device 1929 sn8 x part no. x x x
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 148 preliminary version 0.4 17.3 marking example name rom type device package temperature material SN8P1929qb otp 1929 lqfp 0 ~70 pb-free package SN8P1929qg otp 1929 lqfp 0 ~70 green package 17.4 datecode system x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
SN8P1929 8-bit micro-controller with charge pump regulator, pgia, 16-bit adc sonix technology co., ltd page 149 preliminary version 0.4 sonix reserves the right to make change without further notic e to any products herein to improve reliability, function or design. sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights no r the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other applicati on in which the failure of the sonix product could create a situation where personal injury or death may occur. s hould buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless agains t all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 9f, no. 8, hsien cheng 5th st, chupei city, hsinchu, taiwan r.o.c. tel: 886-3-551 0520 fax: 886-3-551 0523 taipei office: address: 15f-2, no. 171, song ted road, taipei, taiwan r.o.c. tel: 886-2-2759 1980 fax: 886-2-2759 8180 hong kong office: address: flat 3 9/f energy plaza 92 granville road, tsimshatsui east kowloon. tel: 852-2723 8086 fax: 852-2723 9179 technical support by email: sn8fae@sonix.com.tw

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